diff --git "a/verilog_eval_problems.json" "b/verilog_eval_problems.json" new file mode 100644--- /dev/null +++ "b/verilog_eval_problems.json" @@ -0,0 +1,5654 @@ +[ + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_0", + "file": "Prob009_popcount3_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (3 bits)\n - output out (2 bits)\n\nThe module should implement a \"population count\" circuit that counts the\nnumber of '1's in the input vector.\n\n", + "metadata": { + "file_size": 311, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob009_popcount3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_1", + "file": "Prob037_review2015_count1k_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - output q (10 bits)\n\nThe module should implement a counter that counts from 0 to 999,\ninclusive, with a period of 1000 cycles. Assume all sequential logic is\ntriggered on the positive edge of the clock. The reset input is active\nhigh synchronous, and should reset the counter to 0.\n\n", + "metadata": { + "file_size": 469, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob037_review2015_count1k_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_2", + "file": "Prob064_vector3_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a (5 bits)\n - input b (5 bits)\n - input c (5 bits)\n - input d (5 bits)\n - input e (5 bits)\n - input f (5 bits)\n - output w (8 bits)\n - output x (8 bits)\n - output y (8 bits)\n - output z (8 bits)\n\nThe module should concatenate the input vectors together then split them\nup into several output vectors. There are six 5-bit input vectors: a, b,\nc, d, e, and f, for a total of 30 bits of input. There are four 8-bit\noutput vectors: w, x, y, and z, for 32 bits of output. The output should\nbe a concatenation of the input vectors followed by two 1 bits (the two 1\nbits should be in the LSB positions).\n\n", + "metadata": { + "file_size": 767, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob064_vector3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_3", + "file": "Prob047_dff8ar_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n - input d (8 bits)\n - output q (8 bits)\n\nThe module should include 8 D flip-flops with active high asynchronous\nreset. The output should be reset to 0. All DFFs should be triggered by\nthe positive edge of clk.\n\n", + "metadata": { + "file_size": 408, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob047_dff8ar_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_4", + "file": "Prob035_count1to10_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - output q (4 bits)\n\nThe module should implement a decade counter that counts 1 through 10,\ninclusive. Assume all sequential logic is triggered on the positive edge\nof the clock. The reset input is active high synchronous, and should\nreset the counter to 1.\n\n", + "metadata": { + "file_size": 444, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob035_count1to10_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_5", + "file": "problems-temp.txt", + "task_type": "spec_to_rtl", + "content": "Prob001_zero\nProb016_m2014_q4j\nProb030_popcount255\nProb033_ece241_2014_q1c\nProb036_ringer\nProb042_vector4\nProb050_kmap1\nProb060_m2014_q4k\nProb092_gatesv100\nProb098_circuit7\nProb103_circuit2\nProb107_fsm1s\nProb108_rule90\nProb112_always_case2\nProb115_shift18\nProb122_kmap4\nProb127_lemmings1\nProb128_fsm_ps2\nProb135_m2014_q6b\nProb144_conwaylife\n", + "metadata": { + "file_size": 341, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/problems-temp.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_6", + "file": "Prob125_kmap3_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input c\n - input d\n - output out\n\nThe module should implement the Karnaugh map below. d is don't-care,\nwhich means you may choose to output whatever value is convenient.\n\n ab\n cd 01 00 10 11\n 00 | d | 0 | 1 | 1 |\n 01 | 0 | 0 | d | d |\n 11 | 0 | 1 | 1 | 1 |\n 10 | 0 | 1 | 1 | 1 |\n\n", + "metadata": { + "file_size": 491, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob125_kmap3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_7", + "file": "Prob126_circuit6_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a ( 3 bits)\n - output q (16 bits)\n\nThe module should implement a combinational circuit. Read the simulation\nwaveforms to determine what the circuit does, then implement it.\n\n time a q\n 0ns x x\n 5ns x x\n 10ns x x\n 15ns 0 1232\n 20ns 1 aee0\n 25ns 2 27d4\n 30ns 3 5a0e\n 35ns 4 2066\n 40ns 5 64ce\n 45ns 6 c526\n 50ns 7 2f19\n 55ns 0 1232\n 60ns 1 aee0\n 65ns 2 27d4\n 70ns 4 2066\n 75ns 1 aee0\n 80ns 1 aee0\n 85ns 3 5a0e\n 90ns 5 64ce\n\n", + "metadata": { + "file_size": 659, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob126_circuit6_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_8", + "file": "Prob052_gates100_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (100 bits)\n - output out_and\n - output out_or\n - output out_xor\n\nThe module should implement a combinational circuit with 100 inputs,\nin[99:0]. There are 3 outputs:\n\n (1) out_and : output of a 100-input AND gate\n (2) out_or : output of a 100-input OR gate\n (3) out_xor : output of a 100-input XOR gate\n\n", + "metadata": { + "file_size": 475, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob052_gates100_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_9", + "file": "Prob007_wire_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in\n - output out\n\nThe module should behave like a wire.\n\n", + "metadata": { + "file_size": 221, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob007_wire_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_10", + "file": "Prob113_2012_q1g_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input x (4 bits)\n - output f\n\nThe module should implement the function f shown in the Karnaugh map\nbelow.\n\n x[0]x[1]\nx[2]x[3] 00 01 11 10\n 00 | 1 | 0 | 0 | 1 |\n 01 | 0 | 0 | 0 | 0 |\n 11 | 1 | 1 | 1 | 0 |\n 10 | 1 | 1 | 0 | 1 |\n\n", + "metadata": { + "file_size": 421, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob113_2012_q1g_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_11", + "file": "Prob140_fsm_hdlc_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input in\n - output disc\n - output flag\n - output err\n\nSynchronous HDLC framing involves decoding a continuous bit stream of\ndata to look for bit patterns that indicate the beginning and end of\nframes (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a\n\"flag\" that indicate frame boundaries. To avoid the data stream from\naccidentally containing \"flags\", the sender inserts a zero after every 5\nconsecutive 1s which the receiver must detect and discard. We also need\nto signal an error if there are 7 or more consecutive 1s. Create a\nMoore-type finite state machine to recognize these three sequences:\n\n (1) 0111110: Signal a bit needs to be discarded (disc).\n (2) 01111110: Flag the beginning/end of a frame (flag).\n (3) 01111111...: Error (7 or more 1s) (err).\n\nWhen the FSM is reset, it should be in a state that behaves as though the\nprevious input were 0. The reset signal is active high synchronous. The\noutput signals should be asserted for a complete cycle beginning on the\nclock cycle after the condition occurs. Assume all sequential\nlogic is triggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 1302, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob140_fsm_hdlc_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_12", + "file": "Prob034_dff8_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input d (8 bits)\n - output q (8 bits)\n\nThe module should include 8 D flip-flops. All DFFs should be triggered by\nthe positive edge of clock.\n\n", + "metadata": { + "file_size": 318, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob034_dff8_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_13", + "file": "Prob145_circuit8_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clock\n - input a\n - output p\n - output q\n\nThe module should implement a sequential circuit. Read the simulation\nwaveforms to determine what the circuit does, then implement it.\n\n time clock a p q\n 0ns 0 0 x x\n 5ns 0 0 x x\n 10ns 0 0 x x\n 15ns 0 0 x x\n 20ns 0 0 x x\n 25ns 1 0 0 x\n 30ns 1 0 0 x\n 35ns 1 0 0 x\n 40ns 1 0 0 x\n 45ns 1 0 0 x\n 50ns 1 0 0 x\n 55ns 0 0 0 0\n 60ns 0 0 0 0\n 65ns 0 0 0 0\n 70ns 0 1 0 0\n 75ns 0 0 0 0\n 80ns 0 1 0 0\n 85ns 1 0 0 0\n 90ns 1 1 1 0\n 95ns 1 0 0 0\n 100ns 1 1 1 0\n 105ns 1 0 0 0\n 110ns 1 1 1 0\n 115ns 0 0 1 1\n 120ns 0 1 1 1\n 125ns 0 0 1 1\n 130ns 0 1 1 1\n 135ns 0 0 1 1\n 140ns 0 0 1 1\n 145ns 1 0 0 1\n 150ns 1 0 0 1\n 155ns 1 0 0 1\n 160ns 1 0 0 1\n 165ns 1 1 1 1\n 170ns 1 0 0 1\n 175ns 0 1 0 0\n 180ns 0 0 0 0\n 185ns 0 1 0 0\n 190ns 0 0 0 0\n\n", + "metadata": { + "file_size": 1424, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob145_circuit8_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_14", + "file": "Prob131_mt2015_q4_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nModule A implements the boolean function z = (x^y) & x.\n\nModule B can be described by the following simulation waveform:\n\n time x y z\n 0ns 0 0 1\n 5ns 0 0 1\n 10ns 0 0 1\n 15ns 0 0 1\n 20ns 0 0 1\n 25ns 1 0 0\n 30ns 1 0 0\n 35ns 0 1 0\n 40ns 0 1 0\n 45ns 1 1 1\n 50ns 1 1 1\n 55ns 0 0 1\n 60ns 0 1 0\n 65ns 0 1 0\n 70ns 1 1 1\n 75ns 0 1 0\n 80ns 0 1 0\n 85ns 0 1 0\n 90ns 1 0 0\n\nNow consider a top-level module with the following interface:\n\n - input x\n - input y\n - output z\n\nThe module is implemented with two A submodules and two B submodules. The\nfirst input of all four submodules is connect to input 'x', and the\nsecond input of all four submodules is connected to 'y'. The output of\nthe first A submodule is connected to a two-input OR, along with the\noutput of the first B submodule. The second pair of A and B submodules is\nsimilarly connected to an AND gate. The output of the OR and the AND is\nconnected to an XOR, whose output is 'z'.\n\n", + "metadata": { + "file_size": 1015, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob131_mt2015_q4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_15", + "file": "Prob033_ece241_2014_q1c_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a (8 bits)\n - input b (8 bits)\n - output s (8 bits)\n - output overflow\n\nAssume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0].\nThe module should add these numbers to produce s[7:0]. Also compute\nwhether a (signed) overflow has occurred.\n\n", + "metadata": { + "file_size": 422, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob033_ece241_2014_q1c_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_16", + "file": "Prob098_circuit7_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input a\n - output q\n\nThis is a sequential circuit. Read the simulation waveforms to determine\nwhat the circuit does, then implement it.\n\n time clk a q\n 0ns 0 x x\n 5ns 1 0 x\n 10ns 0 0 x\n 15ns 1 0 1\n 20ns 0 0 1\n 25ns 1 0 1\n 30ns 0 0 1\n 35ns 1 1 1\n 40ns 0 1 1\n 45ns 1 1 0\n 50ns 0 1 0\n 55ns 1 1 0\n 60ns 0 1 0\n 65ns 1 1 0\n 70ns 0 1 0\n 75ns 1 1 0\n 80ns 0 1 0\n 85ns 1 1 0\n 90ns 0 1 0\n\nAssume all sequential logic is triggered on the positive edge of the\nclock.\n\n", + "metadata": { + "file_size": 747, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob098_circuit7_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_17", + "file": "Prob075_counter_2bc_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n - input train_valid\n - input train_taken\n - output state (2 bits)\n\nThe module should implement a two-bit saturating counter. The counter\nincrements (up to a maximum of 3) when train_valid = 1 and\ntrain_taken = 1. It decrements (down to a minimum of 0) when\ntrain_valid = 1 and train_taken = 0. When not training (train_valid = 0),\nthe counter keeps its value unchanged. areset is a positive edge\ntriggered asynchronous reset that resets the counter to weakly not-taken\n(2'b01). Output state[1:0] is the two-bit counter value. Assume all\nsequential logic is triggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 791, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob075_counter_2bc_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_18", + "file": "Prob056_ece241_2013_q7_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input j\n - input k\n - output Q\n\nThe module should implement a JK flip-flop with the following truth\ntable. Note: Qold is the output of the flip-flop before the positive\nclock edge.\n\n J | K | Q\n 0 | 0 | Qold\n 0 | 1 | 0\n 1 | 0 | 1\n 1 | 1 | ~Qold\n\n", + "metadata": { + "file_size": 423, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob056_ece241_2013_q7_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_19", + "file": "Prob151_review2015_fsm_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input data\n - input done_counting\n - input ack\n - output shift_ena\n - output counting\n - output done\n\nThe module should implement a timer that:\n\n (1) is started when a particular pattern (1101) is detected,\n (2) shifts in 4 more bits to determine the duration to delay,\n (3) waits for the counters to finish counting, and\n (4) notifies the user and waits for the user to acknowledge the timer.\n\nIn this problem, implement just the finite-state machine that controls\nthe timer. The data path (counters and some comparators) are not included\nhere.\n\nThe serial data is available on the data input pin. When the pattern 1101\nis received, the state machine must then assert output shift_ena for\nexactly 4 clock cycles. After that, the state machine asserts its\ncounting output to indicate it is waiting for the counters, and waits\nuntil input done_counting is high.At that point, the state machine must\nassert done to notify the user the timer has timed out, and waits until\ninput ack is 1 before being reset to look for the next occurrence of the\nstart sequence (1101). The state machine should have a active high\nsynchronous reset, setting the state to where it begins searching for the\ninput sequence 1101. Assume all sequential logic is triggered on the\npositive edge of the clock.\n\n", + "metadata": { + "file_size": 1476, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob151_review2015_fsm_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_20", + "file": "Prob124_rule110_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input load\n - input data (512 bits)\n - output q (512 bits)\n\nThe module should implement Rule 110, a one-dimensional cellular\nautomaton with interesting properties (such as being Turing-complete).\nThere is a one-dimensional array of cells (on or off). At each time step,\nthe state of each cell changes. In Rule 110, the next state of each cell\ndepends only on itself and its two neighbours, according to the following\ntable:\n\n Left[i+1] | Center[i] | Right[i-1] | Center's next state \n 1 | 1 | 1 | 0\n 1 | 1 | 0 | 1\n 1 | 0 | 1 | 1\n 1 | 0 | 0 | 0\n 0 | 1 | 1 | 1\n 0 | 1 | 0 | 1\n 0 | 0 | 1 | 1\n 0 | 0 | 0 | 0\n\nIn this circuit, create a 512-cell system (q[511:0]), and advance by one\ntime step each clock cycle. The synchronous active high load input\nindicates the state of the system should be loaded with data[511:0].\nAssume the boundaries (q[-1] and q[512], if they existed) are both zero\n(off). Assume all sequential logic is triggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 1355, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob124_rule110_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_21", + "file": "Prob087_gates_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - output out_and\n - output out_or\n - output out_xor\n - output out_nand\n - output out_nor\n - output out_xnor\n - output out_anotb\n\nThe module should implement a combinational circuit with two inputs, a\nand b. There are 7 outputs, each with a logic gate driving it:\n\n (1) out_and: a and b\n (2) out_or: a or b\n (3) out_xor: a xor b\n (4) out_nand: a nand b\n (5) out_nor: a nor b\n (6) out_xnor: a xnor b\n (7) out_anotb: a and-not b\n\n", + "metadata": { + "file_size": 613, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob087_gates_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_22", + "file": "Prob065_7420_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input p1a\n - input p1b\n - input p1c\n - input p1d\n - input p2a\n - input p2b\n - input p2c\n - input p2d\n - output p1y\n - output p2y\n\nThe 7400-series integrated circuits are a series of digital chips with a\nfew gates each. The 7420 is a chip with two 4-input NAND gates. The\nmodule should implement the same functionality as the 7420 chip.\n\n", + "metadata": { + "file_size": 502, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob065_7420_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_23", + "file": "Prob084_ece241_2013_q12_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input enable\n - input S\n - input A\n - input B\n - input C\n - output Z\n\nThe module should implement a circuit for an 8x1 memory, where writing to\nthe memory is accomplished by shifting-in bits, and reading is \"random\naccess\", as in a typical RAM. You will then use the circuit to realize a\n3-input logic function. First, create an 8-bit shift register with 8\nD-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7]. The\nshift register input should be called S, which feeds the input of Q[0]\n(MSB is shifted in first). The enable input is synchronous active high\nand controls whether to shift. Extend the circuit to have 3 additional\ninputs A,B,C and an output Z. The circuit's behaviour should be as\nfollows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on.\nYour circuit should contain ONLY the 8-bit shift register, and\nmultiplexers. Assume all sequential logic is triggered on the positive\nedge of the clock.\n\n", + "metadata": { + "file_size": 1106, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob084_ece241_2013_q12_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_24", + "file": "Prob042_vector4_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (8 bits)\n - output out (32 bits)\n\nOne common place to see a replication operator is when sign-extending a\nsmaller number to a larger one, while preserving its signed value. This\nis done by replicating the sign bit (the most significant bit) of the\nsmaller number to the left. For example, sign-extending 4'b0101 (5) to 8\nbits results in 8'b00000101 (5), while sign-extending 4'b1101 (-3) to 8\nbits results in 8'b11111101 (-3). Implement a module that sign-extends an\n8-bit number to 32 bits. This requires a concatenation of 24 copies of\nthe sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit\nnumber itself.\n\n", + "metadata": { + "file_size": 792, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob042_vector4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_25", + "file": "Prob103_circuit2_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input c\n - input d\n - output q\n\nThe module should implement a combinational circuit. Read the simulation\nwaveforms to determine what the circuit does, then implement it.\n\n time a b c d q\n 0ns 0 0 0 0 1\n 5ns 0 0 0 0 1\n 10ns 0 0 0 0 1\n 15ns 0 0 0 0 1\n 20ns 0 0 0 1 0\n 25ns 0 0 1 0 0\n 30ns 0 0 1 1 1\n 35ns 0 1 0 0 0\n 40ns 0 1 0 1 1\n 45ns 0 1 1 0 1\n 50ns 0 1 1 1 0\n 55ns 1 0 0 0 0\n 60ns 1 0 0 1 1\n 65ns 1 0 1 0 1\n 70ns 1 0 1 1 0\n 75ns 1 1 0 0 1\n 80ns 1 1 0 1 0\n 85ns 1 1 1 0 0\n 90ns 1 1 1 1 1\n\n", + "metadata": { + "file_size": 795, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob103_circuit2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_26", + "file": "Prob129_ece241_2013_q8_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input aresetn\n - input x\n - output z\n\nThe module should implement a Mealy-type finite state machine that\nrecognizes the sequence \"101\" on an input signal named x. Your FSM should\nhave an output signal, z, that is asserted to logic-1 when the \"101\"\nsequence is detected. Your FSM should also have a negative edge triggered\nasynchronous reset. You may only have 3 states in your state machine.\nYour FSM should recognize overlapping sequences. Assume all sequential\nlogic is triggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 691, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob129_ece241_2013_q8_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_27", + "file": "Prob133_2014_q3fsm_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input s\n - input w\n - output z\n\nThe module should implement a finite state machine with inputs s and w.\nAssume that the FSM begins in a reset state called A, as depicted below.\nThe FSM remains in state A as long as s = 0, and it moves to state B when\ns = 1. Once in state B the FSM examines the value of the input w in the\nnext three clock cycles. If w = 1 in exactly two of these clock cycles,\nthen the FSM has to set an output z to 1 in the following clock cycle.\nOtherwise z has to be 0. The FSM continues checking w for the next three\nclock cycles, and so on. Use as few states as possible. Note that the s\ninput is used only in state A, so you need to consider just the w input.\nAssume reset is active high synchronous. Assume all sequential logic is\ntriggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 991, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob133_2014_q3fsm_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_28", + "file": "Prob070_ece241_2013_q2_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input c\n - input d\n - output out_sop\n - output out_pos\n\nThe module should implement a digital system with four inputs (a,b,c,d)\nthat generates a logic-1 when 2, 7, or 15 appears on the inputs, and a\nlogic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input\nconditions for the numbers 3, 8, 11, and 12 never occur in this system.\nFor example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively.\nDetermine the output out_sop in minimum sum-of-products form, and the\noutput out_pos in minimum product-of-sums form.\n\n", + "metadata": { + "file_size": 717, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob070_ece241_2013_q2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_29", + "file": "Prob082_lfsr32_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - output q (32 bits)\n\nA linear feedback shift register is a shift register usually with a few\nXOR gates to produce the next state of the shift register. A Galois LFSR\nis one particular arrangement that shifts right, where a bit position with\na \"tap\" is XORed with the LSB output bit (q[0]) to produce its next value,\nwhile bit positions without a tap shift right unchanged. \n\nThe module should implement a 32-bit Galois LFSR with taps at bit\npositions 32, 22, 2, and 1. Reset should be active high synchronous, and\nshould reset the output q to 32'h1. Assume all sequential logic is\ntriggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 813, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob082_lfsr32_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_30", + "file": "Prob071_always_casez_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (8 bits)\n - output pos (3 bits)\n\nThe module should implement a priority encoder for an 8-bit input. Given\nan 8-bit vector, the output should report the first (least significant)\nbit in the vector that is 1. Report zero if the input vector has no bits\nthat are high. For example, the input 8'b10010000 should output 3'd4,\nbecause bit[4] is first bit that is high.\n\n", + "metadata": { + "file_size": 532, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob071_always_casez_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_31", + "file": "Prob135_m2014_q6b_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input y (3 bits)\n - input w\n - output Y1\n\nThe module should implement the state machine shown below:\n\n A (0) --0--> B\n A (0) --1--> A\n B (0) --0--> C\n B (0) --1--> D\n C (0) --0--> E\n C (0) --1--> D\n D (0) --0--> F\n D (0) --1--> A\n E (1) --0--> E\n E (1) --1--> D\n F (1) --0--> C\n F (1) --1--> D\n\nThe FSM should be implemented using three flip-flops and state codes\ny = 000, 001, ..., 101 for states A, B, ..., F, respectively. Implement\njust the next-state logic for y[1]. The output Y1 is y[1].\n\n", + "metadata": { + "file_size": 667, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob135_m2014_q6b_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_32", + "file": "Prob001_zero_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - output zero\n\nThe module should always outputs a LOW.\n\n", + "metadata": { + "file_size": 211, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob001_zero_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_33", + "file": "Prob099_m2014_q6c_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input y (6 bits)\n - input w\n - output Y1\n - output Y3\n\nConsider the state machine shown below:\n\n A (0) --0--> B\n A (0) --1--> A\n B (0) --0--> C\n B (0) --1--> D\n C (0) --0--> E\n C (0) --1--> D\n D (0) --0--> F\n D (0) --1--> A\n E (1) --0--> E\n E (1) --1--> D\n F (1) --0--> C\n F (1) --1--> D\n\nResets into state A. For this part, assume that a one-hot code is used\nwith the state assignment y[5:0] = 000001, 000010, 000100, 001000,\n010000, 100000 for states A, B,..., F, respectively.\n\nThe module shou module ment the next-state signals Y2 and Y4\ncorresponding to signal y[1] and y[3]. Derive the logic equations by\ninspection assuming the one-hot encoding.\n implement the next-state signals and corresponding to\nsignal y[1] and y[3]Derive the logic equations byinspection assuming the one-hot encoding.\n\n", + "metadata": { + "file_size": 972, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob099_m2014_q6c_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_34", + "file": "Prob083_mt2015_q4b_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input x\n - input y\n - output z\n\nThe module can be described by the following simulation waveform:\n\n time x y z\n 0ns 0 0 1\n 5ns 0 0 1\n 10ns 0 0 1\n 15ns 0 0 1\n 20ns 0 0 1\n 25ns 1 0 0\n 30ns 1 0 0\n 35ns 0 1 0\n 40ns 0 1 0\n 45ns 1 1 1\n 50ns 1 1 1\n 55ns 0 0 1\n 60ns 0 1 0\n 65ns 0 1 0\n 70ns 1 1 1\n 75ns 0 1 0\n 80ns 0 1 0\n 85ns 0 1 0\n 90ns 1 0 0\n\n", + "metadata": { + "file_size": 579, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob083_mt2015_q4b_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_35", + "file": "Prob069_truthtable1_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input x3\n - input x2\n - input x1\n - output f\n\nThe module should implement a combinational circuit for the following\ntruth table:\n\n x3 | x2 | x1 | f\n 0 | 0 | 0 | 0\n 0 | 0 | 1 | 0\n 0 | 1 | 0 | 1\n 0 | 1 | 1 | 1\n 1 | 0 | 0 | 0\n 1 | 0 | 1 | 1\n 1 | 1 | 0 | 0\n 1 | 1 | 1 | 1\n\n", + "metadata": { + "file_size": 462, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob069_truthtable1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_36", + "file": "Prob139_2013_q2bfsm_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input resetn\n - input x\n - input y\n - output f\n - output g\n\nConsider a finite state machine that is used to control some type of\nmotor. The FSM has inputs x and y, which come from the motor, and\nproduces outputs f and g, which control the motor. There is also a clock\ninput called clk and a reset input (synchronous, active low) called\nresetn. The FSM has to work as follows. As long as the reset input is\nasserted, the FSM stays in a beginning state, called state A. When the\nreset signal is de-asserted, then after the next clock edge the FSM has\nto set the output f to 1 for one clock cycle. Then, the FSM has to\nmonitor the x input. When x has produced the values 1, 0, 1 in three\nsuccessive clock cycles, then g should be set to 1 on the following clock\ncycle. While maintaining g = 1 the FSM has to monitor the y input. If y\nhas the value 1 within at most two clock cycles, then the FSM should\nmaintain g = 1 permanently (that is, until reset). But if y does not\nbecome 1 within two clock cycles, then the FSM should set g = 0\npermanently (until reset). Assume all sequential logic is triggered on\nthe positive edge of the clock.\n\n", + "metadata": { + "file_size": 1311, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob139_2013_q2bfsm_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_37", + "file": "Prob080_timer_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk,\n - input load,\n - input data (10 bits)\n - output tc\n\nThe module should implement a timer that counts down for a given number\nof clock cycles, then asserts a signal to indicate that the given\nduration has elapsed. A good way to implement this is with a down-counter\nthat asserts an output signal when the count becomes 0. At each clock\ncycle:\n\n (1) If load = 1, load the internal counter with the 10-bit data, the\n number of clock cycles the timer should count before timing out. The\n counter can be loaded at any time, including when it is still counting\n and has not yet reached 0.\n\n (2) If load = 0, the internal counter should decrement by 1. The output\n signal tc (\"terminal count\") indicates whether the internal counter has\n reached 0. Once the internal counter has reached 0, it should stay 0\n (stop counting) until the counter is loaded again.\n\nThe module should implement a single D flip-flop. Assume all sequential\nlogic is triggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 1159, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob080_timer_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_38", + "file": "Prob104_mt2015_muxdff_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input L\n - input q_in\n - input r_in\n - output Q\n\nConsider this Verilog module \"full_module\":\n\n module full_module (\n input [2:0] r,\n input L,\n input clk,\n output reg [2:0] q);\n\n always @(posedge clk) begin\n if (L) begin\n q <= r;\n end else begin\n q <= {q[1] ^ q[2], q[0], q[2]};\n end\n end\n\n endmodule\n\nNote that q[2:0] is three bits wide, representing three flip-flops that can be\nloaded from r when L is asserted. You want to factor full_module into a hierarchical\ndesign, flipflop and 2:1 multiplexer are in a submodule \"TopModule\", and that submodule\nwill be instantiated three times in full_module code. Create the submodule called \"TopModule\".\nYou do not have to provide the revised full_module.\n\n", + "metadata": { + "file_size": 932, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob104_mt2015_muxdff_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_39", + "file": "Prob107_fsm1s_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input in\n - output out\n\nImplement the following Moore state machine with two states, one input,\nand one output. The reset state is B and reset is active-high\nsynchronous.\n\n B (out=1) --in=0--> A\n B (out=1) --in=1--> B\n A (out=0) --in=0--> B\n A (out=0) --in=1--> A\n\n", + "metadata": { + "file_size": 457, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob107_fsm1s_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_40", + "file": "Prob110_fsm2_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n - input j\n - input k\n - output out\n\nThe module should implement a Moore state machine with two states, two\ninputs, and one output according to diagram described below. Reset is an\nactive-high asynchronous reset to state OFF.\n\n OFF (out=0) --j=0--> OFF\n OFF (out=0) --j=1--> ON\n ON (out=1) --k=0--> ON\n ON (out=1) --k=1--> OFF\n\n", + "metadata": { + "file_size": 521, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob110_fsm2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_41", + "file": "Prob155_lemmings4_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n - input bump_left\n - input bump_right\n - input ground\n - input dig\n - output walk_left\n - output walk_right\n - output aaah\n - output digging\n\nThe game Lemmings involves critters with fairly simple brains. So simple\nthat we are going to model it using a finite state machine. In the\nLemmings' 2D world, Lemmings can be in one of two states: walking left\n(walk_left is 1) or walking right (walk_right is 1). It will switch\ndirections if it hits an obstacle. In particular, if a Lemming is bumped\non the left (by receiving a 1 on bump_left), it will walk right. If it's\nbumped on the right (by receiving a 1 on bump_right), it will walk left.\nIf it's bumped on both sides at the same time, it will still switch\ndirections.\n\nIn addition to walking left and right and changing direction when bumped,\nwhen ground=0, the Lemming will fall and say \"\"aaah!\"\". When the ground\nreappears (ground=1), the Lemming will resume walking in the same\ndirection as before the fall. Being bumped while falling does not affect\nthe walking direction, and being bumped in the same cycle as ground\ndisappears (but not yet falling), or when the ground reappears while\nstill falling, also does not affect the walking direction.\n\nIn addition to walking and falling, Lemmings can sometimes be told to do\nuseful things, like dig (it starts digging when dig=1). A Lemming can dig\nif it is currently walking on ground (ground=1 and not falling), and will\ncontinue digging until it reaches the other side (ground=0). At that\npoint, since there is no ground, it will fall (aaah!), then continue\nwalking in its original direction once it hits ground again. As with\nfalling, being bumped while digging has no effect, and being told to dig\nwhen falling or when there is no ground is ignored. (In other words, a\nwalking Lemming can fall, dig, or switch directions. If more than one of\nthese conditions are satisfied, fall has higher precedence than dig,\nwhich has higher precedence than switching directions.)\n\nAlthough Lemmings can walk, fall, and dig, Lemmings aren't invulnerable.\nIf a Lemming falls for too long then hits the ground, it can splatter. In\nparticular, if a Lemming falls for more than 20 clock cycles then hits\nthe ground, it will splatter and cease walking, falling, or digging (all\n4 outputs become 0), forever (Or until the FSM gets reset). There is no\nupper limit on how far a Lemming can fall before hitting the ground.\nLemmings only splatter when hitting the ground; they do not splatter in\nmid-air.\n\nImplement a Moore state machine that models this behaviour. areset is\npositive edge triggered asynchronous reseting the Lemming machine to walk\nleft.\n\nAssume all sequential logic is triggered on the positive edge of the\nclock.\n\n", + "metadata": { + "file_size": 2906, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob155_lemmings4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_42", + "file": "Prob013_m2014_q4e_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in1\n - input in2\n - output out\n\nThe module should implement a 2-input NOR gate.\n\n", + "metadata": { + "file_size": 246, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob013_m2014_q4e_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_43", + "file": "Prob148_2013_q2afsm_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input resetn\n - input r (3 bits)\n - output g (3 bits)\n\nThe module should implement the FSM described by the state diagram shown\nbelow:\n\n A --r0=0,r1=0,r2=0--> A\n A -------r0=1-------> B\n A -----r0=0,r1=1----> C\n A --r0=0,r1=0,r2=0--> D\n B (g0=1) -------r0=1-------> B\n B (g0=1) -------r0=0-------> A\n C (g1=1) -------r1=1-------> C\n C (g1=1) -------r1=0-------> A\n\nResetn is an active-low synchronous reset that resets into state A. This\nFSM acts as an arbiter circuit, which controls access to some type of\nresource by three requesting devices. Each device makes its request for\nthe resource by setting a signal _r[i]_ = 1, where _r[i]_ is either\n_r[0]_, _r[1]_, or _r[2]_. Each r[i] is an input signal to the FSM, and\nrepresents one of the three devices. The FSM stays in state _A_ as long\nas there are no requests. When one or more request occurs, then the FSM\ndecides which device receives a grant to use the resource and changes to\na state that sets that device's _g[i]_ signal to 1. Each _g[i]_ is an\noutput from the FSM. There is a priority system, in that device 0 has a\nhigher priority than device 1, and device 2 has the lowest priority.\nHence, for example, device 2 will only receive a grant if it is the only\ndevice making a request when the FSM is in state _A_. Once a device, _i_,\nis given a grant by the FSM, that device continues to receive the grant\nas long as its request, _r[i]_ = 1.\n\nImplement a module that represents this FSM. Use separate always blocks\nfor the state table and the state flip-flops, as done in lectures.\nDescribe the FSM outputs, _g[i]_, using either continuous assignment\nstatement(s) or an always block (at your discretion). Assign any state\ncodes that you wish to use. Assume all sequential logic is triggered on\nthe positive edge of the clock.\n\n", + "metadata": { + "file_size": 1997, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob148_2013_q2afsm_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_44", + "file": "Prob077_wire_decl_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input c\n - input d\n - output out\n - output out_n\n\nThe module should implement the following circuit. Create two\nintermediate wires (named anything you want) to connect the AND and OR\ngates together. Note that the wire that feeds the NOT gate is really wire\n`out`, so you do not necessarily need to declare a third wire here.\nNotice how wires are driven by exactly one source (output of a gate), but\ncan feed multiple inputs.\n\nThe circuit is composed of two layers. The first layer, counting from the\ninput, is two AND gates: one whose input is connected to a and b, and the\nsecond is connected to c and d. The second layer there is an OR gate to\nOR the two AND outputs, connected the output 'out'. Additionally, there\nis an inverted output 'out_n'.\n\n", + "metadata": { + "file_size": 933, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob077_wire_decl_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_45", + "file": "Prob081_7458_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input p1a\n - input p1b\n - input p1c\n - input p1d\n - input p1e\n - input p1f\n - input p2a\n - input p2b\n - input p2c\n - input p2d\n - output p1y\n - output p2y\n\nThe 7458 is a chip with four AND gates and two OR gates. Implement a\nmodule with the same functionality as the 7458 chip. It has 10 inputs and\n2 outputs. You may choose to use an `assign` statement to drive each of\nthe output wires, or you may choose to declare (four) wires for use as\nintermediate signals, where each internal wire is driven by the output of\none of the AND gates.\n\nIn this circuit, p1y should be the OR of two 3-input AND gates: one that\nANDs p1a, p1b, and p1c, and the second that ANDs p1d, p1e, and p1f. The\noutput p2y is the OR of two 2-input AND gates: one that ANDs p2a and p2b,\nand the second that ANDs p2c and p2d.\n\n", + "metadata": { + "file_size": 964, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob081_7458_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_46", + "file": "Prob120_fsm3s_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input in\n - output out\n\nThe module should implement a Moore state machine with the following\nstate transition table with one input, one output, and four states.\nInclude a synchronous active high reset that resets the FSM to state A.\nAssume all sequential logic is triggered on the positive edge of the\nclock.\n\n State | Next state in=0, Next state in=1 | Output\n A | A, B | 0\n B | C, B | 0\n C | A, D | 0\n D | C, B | 1\n\n", + "metadata": { + "file_size": 739, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob120_fsm3s_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_47", + "file": "Prob143_fsm_onehot_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in\n - input state (10 bits)\n - output next_state (10 bits)\n - output out1\n - output out2\n\nGiven the follow state machine with 1 input and 2 outputs (the outputs\nare given as \"(out1, out2)\"):\n\n S0 (0, 0) --0--> S0\n S0 (0, 0) --1--> S1\n S1 (0, 0) --0--> S0\n S1 (0, 0) --1--> S2\n S2 (0, 0) --0--> S0\n S2 (0, 0) --1--> S3\n S3 (0, 0) --0--> S0\n S3 (0, 0) --1--> S4\n S4 (0, 0) --0--> S0\n S4 (0, 0) --1--> S5\n S5 (0, 0) --0--> S8\n S5 (0, 0) --1--> S6\n S6 (0, 0) --0--> S9\n S6 (0, 0) --1--> S7\n S7 (0, 1) --0--> S0\n S7 (0, 1) --1--> S7\n S8 (1, 0) --0--> S0\n S8 (1, 0) --1--> S1\n S9 (1, 1) --0--> S0\n S9 (1, 1) --1--> S1\n\nSuppose this state machine uses one-hot encoding, where state[0] through\nstate[9] correspond to the states S0 though S9, respectively. The outputs\nare zero unless otherwise specified. The next_state[0] through next_state[9] \ncorrespond to the transition to next states S0 though S9. For example, The \nnext_state[1] is set to 1 when the next state is S1 , otherwise, it is set to 0.\n\nHere, the input state[9:0] can be a combinational of multiple states, and \nthe TopModule is expected to response.\nFor example: \nWhen the state[9:0] = 10'b0000010100, state[4] == 1, and state[2] == 1, the \nstates includes S4, and S2 states.\n\nThe module should implement the state transition logic and output logic\nportions of the state machine (but not the state flip-flops). You are\ngiven the current state in state[9:0] and must implement next_state[9:0] \nand the two outputs.\n\n", + "metadata": { + "file_size": 1660, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob143_fsm_onehot_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_48", + "file": "Prob051_gates4_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (4 bits)\n - output out_and\n - output out_or\n - output out_xor\n\nThe module should implement a combinational circuit with four inputs,\nin[3:0]. There are 3 outputs:\n\n (1) out_and : output of a 4-input AND gate\n (2) out_or : output of a 4-input OR gate\n (3) out_xor : output of a 4-input XOR gate\n\n", + "metadata": { + "file_size": 467, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob051_gates4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_49", + "file": "Prob095_review2015_fsmshift_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - output shift_ena\n\nThis module is a part of the FSM for controlling a shift register, we\nwant the ability to enable the shift register for exactly 4 clock cycles\nwhenever the proper bit pattern is detected. Whenever the FSM is reset,\nassert shift_ena for 4 cycles, then 0 forever (until reset). Reset should\nbe active high synchronous.\n\nAssume all sequential logic is triggered on the positive edge of the\nclock.\n\n", + "metadata": { + "file_size": 600, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob095_review2015_fsmshift_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_50", + "file": "Prob021_mux256to1v_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (1024 bits)\n - input sel ( 8 bits)\n - output out ( 4 bits)\n\nThe module should implement a 4-bit wide, 256-to-1 multiplexer. The 256\n4-bit inputs are all packed into a single 1024-bit input vector. sel=0\nshould select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects\nbits in[11:8], etc.\n\n", + "metadata": { + "file_size": 467, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob021_mux256to1v_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_51", + "file": "Prob002_m2014_q4i_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - output out\n\nThe module should always drive 0 (or logic low).\n\n", + "metadata": { + "file_size": 219, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob002_m2014_q4i_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_52", + "file": "Prob006_vectorr_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (8 bits)\n - output out (8 bits)\n\nThe module should reverse the bit ordering of the input port and write\nthe result to the output port.\n\n", + "metadata": { + "file_size": 304, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob006_vectorr_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_53", + "file": "Prob074_ece241_2014_q4_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input x\n - output z\n\nThe module should implement a finite state machine with the following\nbehavior. Input x goes to three different two-input gates: an XOR, an\nAND, and a OR gate. Each of the three gates is connected to the input of\na D flip-flop and then the flip-flop outputs all go to a three-input\nNOR gate, whose output is Z. The second input of the XOR is its corresponding\nflip-flop's output, the second input of the AND is its corresponding\nflip-flop's complemented output, and finally the second input of the OR\nis its corresponding flip-flop's complementary output.\n\nAssume that the D flip-flops are initially reset to zero before the\nmachine begins. Assume all sequential logic is triggered on the positive\nedge of the clock.\n\n", + "metadata": { + "file_size": 911, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob074_ece241_2014_q4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_54", + "file": "Prob127_lemmings1_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n - input bump_left\n - input bump_right\n - output walk_left\n - output walk_right\n\nThe module should implement a simple game called Lemmings which involves\ncritters with fairly simple brains. So simple that we are going to model\nit using a finite state machine. In the Lemmings' 2D world, Lemmings can\nbe in one of two states: walking left (walk_left is 1) or walking right\n(walk_right is 1). It will switch directions if it hits an obstacle. In\nparticular, if a Lemming is bumped on the left (by receiving a 1 on\nbump_left), it will walk right. If it's bumped on the right (by receiving\na 1 on bump_right), it will walk left. If it's bumped on both sides at\nthe same time, it will still switch directions.\n\nThe module should implement a Moore state machine with two states, two\ninputs, and one output (internal to the module) that models this\nbehaviour. areset is positive edge triggered asynchronous resetting the\nLemming machine to walk left. Assume all sequential logic is triggered on\nthe positive edge of the clock.\n\n", + "metadata": { + "file_size": 1208, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob127_lemmings1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_55", + "file": "Prob010_mt2015_q4a_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input x\n - input y\n - output z\n\nThe module should implement the boolean function z = (x^y) & x.\n\n", + "metadata": { + "file_size": 256, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob010_mt2015_q4a_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_56", + "file": "Prob141_count_clock_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input ena\n - output pm\n - output hh (8 bits)\n - output mm (8 bits)\n - output ss (8 bits)\n\nCreate a set of counters suitable for use as a 12-hour clock (with am/pm\nindicator). Your counters are clocked by a fast-running clk, with a pulse\non ena whenever your clock should increment (i.e., once per second, while\n\"clk\" is much faster than once per second). The signal \"pm\" is asserted\nif the clock is PM, or is otherwise AM. hh, mm, and ss are two BCD\n(Binary- Coded Decimal) digits each for hours (01-12), minutes (00-59),\nand seconds (00-59). Reset is the active high synchronous signal that\nresets the clock to \"12:00 AM.\" Reset has higher priority than enable and\ncan occur even when not enabled. Assume all sequential logic is triggered\non the positive edge of the clock.\n\n", + "metadata": { + "file_size": 964, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob141_count_clock_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_57", + "file": "Prob128_fsm_ps2_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input in (8 bits)\n - output done\n\nThe PS/2 mouse protocol sends messages that are three bytes long.\nHowever, within a continuous byte stream, it's not obvious where messages\nstart and end. The only indication is that the first byte of each three\nbyte message always has in[3]=1 (but in[3] of the other two bytes may be\n1 or 0 depending on data).\n\nThe module should implement a finite state machine that will search for\nmessage boundaries when given an input byte stream. The algorithm we'll\nuse is to discard bytes until we see one with in[3]=1. We then assume\nthat this is byte 1 of a message, and signal the receipt of a message\nonce all 3 bytes have been received (done). The FSM should signal done in\nthe cycle immediately after the third byte of each message was\nsuccessfully received. Reset should be active high synchronous. Assume\nall sequential logic is triggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 1097, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob128_fsm_ps2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_58", + "file": "Prob112_always_case2_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (4 bits)\n - output pos (2 bits)\n\nThe module should implement a priority encoder. A priority encoder is a\ncombinational circuit that, when given an input bit vector, outputs the\nposition of the first 1 bit in the vector. For example, a 8-bit priority\nencoder given the input 8'b10010000 would output 3'd4, because bit[4] is\nfirst bit that is high. Build a 4-bit priority encoder. For this problem,\nif none of the input bits are high (i.e., input is zero), output zero.\nNote that a 4-bit number has 16 possible combinations.\n\n", + "metadata": { + "file_size": 692, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob112_always_case2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_59", + "file": "Prob043_vector5_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input c\n - input d\n - input e\n - output out (25 bits)\n\nImplement a module that given five 1-bit signals (a, b, c, d, and e),\ncompute all 25 pairwise one-bit comparisons in the 25-bit output vector.\nThe output should be 1 if the two bits being compared are equal. Example:\nout[24] = ~a ^ a; out[23] = ~a ^ b; out[22] = ~a ^ c; ...\nout[ 1] = ~e ^ d; out[ 0] = ~e ^ e.\n\n", + "metadata": { + "file_size": 551, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob043_vector5_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_60", + "file": "Prob058_alwaysblock2_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input a\n - input b\n - output out_assign\n - output out_always_comb\n - output out_always_ff\n\nThe module should implement an XOR gate three ways, using an assign\nstatement (output out_assign), a combinational always block (output\nout_always_comb), and a clocked always block (output out_always_ff). Note\nthat the clocked always block produces a different circuit from the other\ntwo: There is a flip- flop so the output is delayed. Assume all\nsequential logic is triggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 678, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob058_alwaysblock2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_61", + "file": "Prob028_m2014_q4a_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input d\n - input ena\n - output q\n\nThe module should impement a D latch using an always block.\n\n", + "metadata": { + "file_size": 254, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob028_m2014_q4a_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_62", + "file": "Prob045_edgedetect2_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input in (8 bits)\n - output anyedge (8 bits)\n\nImplement a module that for each bit in an 8-bit input vector, detect\nwhen the input signal changes from one clock cycle to the next (detect\nany edge). The output bit of anyedge should be set to 1 the cycle \nafter the input bit has 0 to 1 or 1 to 0 transition occurs. Assume all \nsequential logic is triggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 568, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob045_edgedetect2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_63", + "file": "Prob108_rule90_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk,\n - input load,\n - input data (512 bits)\n - output q (512 bits)\n\nThe module should implement Rule 90, a one-dimensional cellular automaton\nwith interesting properties. The rules are simple. There is a\none-dimensional array of cells (on or off). At each time step, the next\nstate of each cell is the XOR of the cell's two current neighbours:\n\n Left | Center | Right | Center's next state\n 1 | 1 | 1 | 0\n 1 | 1 | 0 | 1\n 1 | 0 | 1 | 0\n 1 | 0 | 0 | 1\n 0 | 1 | 1 | 1\n 0 | 1 | 0 | 0\n 0 | 0 | 1 | 1\n 0 | 0 | 0 | 0\n\nIn this circuit, create a 512-cell system (q[511:0]), and advance by one\ntime step each clock cycle. The load input indicates the state of the\nsystem should be loaded with data[511:0]. Assume the boundaries (q[-1]\nand q[512]) are both zero (off). Assume all sequential logic is triggered\non the positive edge of the clock.\n\n", + "metadata": { + "file_size": 1110, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob108_rule90_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_64", + "file": "Prob030_popcount255_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (255 bits)\n - output out ( 8 bits)\n\nA \"population count\" circuit counts the number of '1's in an input\nvector. The module should implement a population count circuit for a\n255-bit input vector.\n\n", + "metadata": { + "file_size": 364, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob030_popcount255_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_65", + "file": "Prob086_lfsr5_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - output q (5 bits)\n\nA linear feedback shift register is a shift register usually with a few\nXOR gates to produce the next state of the shift register. A Galois LFSR\nis one particular arrangement that shifts right, where a bit position with\na \"tap\" is XORed with the LSB output bit (q[0]) to produce its next value,\nwhile bit positions without a tap shift right unchanged. If the taps positions\nare carefully chosen, the LFSR can be made to be \"maximum-length\". A maximum-length\nLFSR of n bits cycles through 2**n-1 states before repeating (the all-zero state is\nnever reached).\n\nThe module should implement a 5-bit maximal-length Galois LFSR with taps\nat bit positions 5 and 3. The active-high synchronous reset should reset\nthe LFSR output to 1. Assume all sequential logic is triggered on the\npositive edge of the clock.\n\n", + "metadata": { + "file_size": 1011, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob086_lfsr5_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_66", + "file": "Prob156_review2015_fancytimer_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input data\n - output count (4 bits)\n - output counting\n - output done\n - input ack\n\nThe module should implement a timer with one input that:\n\n (1) is started when a particular input pattern (1101) is detected,\n (2) shifts in 4 more bits to determine the duration to delay,\n (3) waits for the counters to finish counting, and\n (4) notifies the user and waits for the user to acknowledge the timer.\n\nThe serial data is available on the data input pin. When the pattern 1101\nis received, the circuit must then shift in the next 4 bits,\nmost-significant-bit first. These 4 bits determine the duration of the\ntimer delay, referred to as delay[3:0]. After that, the state machine\nasserts its counting output to indicate it is counting. Once the 1101 and\ndelay[3:0] have been read, the circuit no longer looks at the data input\nuntil it resumes searching after everything else is done.\n\nThe state machine must count for exactly (delay[3:0] + 1) * 1000 clock\ncycles. e.g., delay=0 means count 1000 cycles, and delay=5 means count\n6000 cycles. Also output the current remaining time. This should be equal\nto delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until\nit is 0 for 1000 cycles.\n\nWhen the circuit isn't counting, the count[3:0] output is don't-care\n(whatever value is convenient for you to implement). At that point, the\ncircuit must assert done to notify the user the timer has timed out, and\nwaits until input ack is 1 before being reset to look for the next\noccurrence of the start sequence (1101).\n\nThe circuit should reset into a state where it begins searching for the\ninput sequence 1101. The reset signal is active high synchronous. Assume\nall sequential logic is triggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 1925, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob156_review2015_fancytimer_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_67", + "file": "Prob055_conditional_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a (8 bits)\n - input b (8 bits)\n - input c (8 bits)\n - input d (8 bits)\n - output min (8 bits)\n\nThe module should find the minimum of the four input values. Unsigned\nnumbers can be compared with standard comparison operators (a < b).\n\n", + "metadata": { + "file_size": 409, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob055_conditional_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_68", + "file": "Prob079_fsm3onehot_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in\n - input state (4 bits)\n - output next_state (4 bits)\n - output out\n\nThe module should implement the state transition table for a Moore state\nmachine with one input, one output, and four states. Use the following\none-hot state encoding: A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000.\nDerive state transition and output logic equations by inspection assuming\na one-hot encoding. Implement only the state transition logic and output\nlogic (the combinational logic portion) for this state machine.\n\n State | Next state in=0, Next state in=1 | Output\n A | A, B | 0\n B | C, B | 0\n C | A, D | 0\n D | C, B | 1\n\n", + "metadata": { + "file_size": 902, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob079_fsm3onehot_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_69", + "file": "Prob016_m2014_q4j_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input x (4 bits)\n - input y (4 bits)\n - output sum (5 bits)\n\nImplement a 4-bit adder with full adders. The output sum should include\nthe overflow bit.\n\n", + "metadata": { + "file_size": 315, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob016_m2014_q4j_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_70", + "file": "Prob073_dff16e_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input resetn\n - input byteena ( 2 bits)\n - input d (16 bits)\n - output q (16 bits)\n\nThe module should include 16 D flip-flops. It's sometimes useful to only\nmodify parts of a group of flip-flops. The byte-enable inputs control\nwhether each byte of the 16 registers should be written to on that cycle.\nbyteena[1] controls the upper byte d[15:8], while byteena[0] controls the\nlower byte d[7:0]. resetn is a synchronous, active-low reset. All DFFs\nshould be triggered by the positive edge of clk.\n\n", + "metadata": { + "file_size": 682, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob073_dff16e_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_71", + "file": "Prob048_m2014_q4c_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input d\n - input r\n - output q\n\nThe module should implement a simple D flip flop with active high\nsynchronous reset (reset output to 0).\n\n", + "metadata": { + "file_size": 311, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob048_m2014_q4c_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_72", + "file": "Prob014_andgate_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - output out\n\nThe module should implement a 2-input AND gate.\n\n", + "metadata": { + "file_size": 242, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob014_andgate_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_73", + "file": "Prob116_m2014_q3_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input x (4 bits)\n - output f\n\nThe module should implement the function f shown in the Karnaugh map\nbelow. d is don't-care, which means you may choose to output whatever\nvalue is convenient.\n\n x[1]x[2]\n x[3]x[4] 00 01 11 10\n 00 | d | 0 | d | d |\n 01 | 0 | d | 1 | 0 |\n 11 | 1 | 1 | d | d |\n 10 | 1 | 1 | 0 | d |\n\n", + "metadata": { + "file_size": 519, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob116_m2014_q3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_74", + "file": "Prob005_notgate_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in\n - output out\n\nThe module should implement a NOT gate.\n\n", + "metadata": { + "file_size": 223, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob005_notgate_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_75", + "file": "Prob144_conwaylife_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input load\n - input data (256 bits)\n - output q (256 bits)\n\nThe module should implemement a \"game\" played on a two-dimensional grid\nof cells, where each cell is either 1 (alive) or 0 (dead). At each time\nstep, each cell changes state depending on how many neighbours it has:\n\n (1) 0-1 neighbour: Cell becomes 0.\n (2) 2 neighbours: Cell state does not change.\n (3) 3 neighbours: Cell becomes 1.\n (4) 4+ neighbours: Cell becomes 0.\n\nThe game is formulated for an infinite grid. In this circuit, we will use\na 16x16 grid. To make things more interesting, we will use a 16x16\ntoroid, where the sides wrap around to the other side of the grid. For\nexample, the corner cell (0,0) has 8 neighbours: (15,1), (15,0), (15,15),\n(0,1), (0,15), (1,1), (1,0), and (1,15). The 16x16 grid is represented by\na length 256 vector, where each row of 16 cells is represented by a\nsub-vector: q[15:0] is row 0, q[31:16] is row 1, etc.\n\n (1) load: Loads data into q at the next clock edge, for loading initial\n state. Active high synchronous.\n (2) q: The 16x16 current state of the game, updated every clock cycle.\n\nThe game state should advance by one timestep every clock cycle. Assume\nall sequential logic is triggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 1420, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob144_conwaylife_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_76", + "file": "Prob147_circuit10_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input a\n - input b\n - output q\n - output state\n\nThe module should implement a sequential circuit. The circuit consists of\ncombinational logic and one bit of memory (i.e., one flip-flop). The\noutput of the flip-flop has been made observable through the output\nstate. Assume all sequential logic is triggered on the positive edge of\nthe clock.\n\nRead the simulation waveforms to determine what the circuit does, then\nimplement it.\n\n time clk a b state q\n 0ns 0 1 x x x\n 5ns 1 1 x x x\n 10ns 0 0 0 x x\n 15ns 1 0 0 0 0\n 20ns 0 0 0 0 0\n 25ns 1 0 0 0 0\n 30ns 0 0 0 0 0\n 35ns 1 0 0 0 0\n 40ns 0 0 0 0 0\n 45ns 1 0 1 0 1\n 50ns 0 0 1 0 1\n 55ns 1 1 0 0 1\n 60ns 0 1 0 0 1\n 65ns 1 1 1 0 0\n 70ns 0 1 1 0 0\n 75ns 1 0 0 1 1\n 80ns 0 0 0 1 1\n 85ns 1 1 1 0 0\n 90ns 0 1 1 0 0\n 95ns 1 1 1 1 1\n 100ns 0 1 1 1 1\n 105ns 1 1 1 1 1\n 110ns 0 1 1 1 1\n 115ns 1 1 0 1 0\n 120ns 0 1 0 1 0\n 125ns 1 0 1 1 0\n 130ns 0 0 1 1 0\n 135ns 1 0 0 1 1\n 140ns 0 0 0 1 1\n 145ns 1 0 0 0 0\n 150ns 0 0 0 0 0\n 155ns 1 0 0 0 0\n 160ns 0 0 0 0 0\n 165ns 1 0 0 0 0\n 170ns 0 0 0 0 0\n 175ns 1 0 0 0 0\n 180ns 0 0 0 0 0\n 185ns 1 0 0 0 0\n 190ns 0 0 0 0 0\n\n", + "metadata": { + "file_size": 1763, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob147_circuit10_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_77", + "file": "Prob091_2012_q2b_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input y (6 bits)\n - input w\n - output Y1\n - output Y3\n\nConsider the following finite-state machine:\n\n A (0) --1--> B\n A (0) --0--> A\n B (0) --1--> C\n B (0) --0--> D\n C (0) --1--> E\n C (0) --0--> D\n D (0) --1--> F\n D (0) --0--> A\n E (1) --1--> E\n E (1) --0--> D\n F (1) --1--> C\n F (1) --0--> D\n\nAssume that a one-hot code is used with the state assignment y[5:0] =\n000001(A), 000010(B), 000100(C), 001000(D), 010000(E), 100000(F)\n\nThe module should implement the state output logic for this finite-state\nmachine. The output signal Y1 should be the input of state flip-flop\ny[1]. The output signal Y3 should be the input of state flip-flop y[3].\nDerive the implementation by inspection assuming the above one-hot\nencoding.\n\n", + "metadata": { + "file_size": 893, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob091_2012_q2b_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_78", + "file": "Prob024_hadd_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - output sum\n - output cout\n\nThe module should implement a half adder. A half adder adds two bits\n(with no carry-in) and produces a sum and carry-out.\n\n", + "metadata": { + "file_size": 331, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob024_hadd_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_79", + "file": "Prob046_dff8p_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input d (8 bits)\n - output q (8 bits)\n\nImplement a module that includes 8 D flip-flops with active high\nsynchronous reset. The flip-flops must be reset to 0x34 rather than zero.\nAll DFFs should be triggered by the negative edge of clk.\n\n", + "metadata": { + "file_size": 425, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob046_dff8p_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_80", + "file": "Prob031_dff_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input d\n - input q\n\nThe module should implement a single D flip-flop. Assume all sequential\nlogic is triggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 317, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob031_dff_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_81", + "file": "Prob044_vectorgates_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a (3 bits)\n - input b (3 bits)\n - output out_or_bitwise (3 bits)\n - output out_or_logical\n - output out_not (6 bits)\n\nImplement a module with two 3-bit inputs that computes the bitwise-OR of\nthe two vectors, the logical-OR of the two vectors, and the inverse (NOT)\nof both vectors. Place the inverse of b in the upper half of out_not\n(i.e., bits [5:3]), and the inverse of a in the lower half.\n\n", + "metadata": { + "file_size": 593, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob044_vectorgates_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_82", + "file": "Prob088_ece241_2014_q5b_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n - input x\n - output z\n\nThe module should implement the following Mealy finite-state machine\nwhich is an implementation of the 2's complementer. Implement using a\none-hot encoding. Resets into state A and reset is asynchronous\nactive-high.\n\n A --x=0 (z=0)--> A\n A --x=1 (z=1)--> B\n B --x=0 (z=1)--> B\n B --x=1 (z=0)--> B\n\nAssume all sequential logic is triggered on the positive edge of the\nclock.\n\n", + "metadata": { + "file_size": 589, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob088_ece241_2014_q5b_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_83", + "file": "Prob017_mux2to1v_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a (100 bits)\n - input b (100 bits)\n - input sel\n - output out (100 bits)\n\nThe module should implement a 2-1 multiplexer. When sel=0, choose a. When\nsel=1, choose b.\n\n", + "metadata": { + "file_size": 336, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob017_mux2to1v_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_84", + "file": "Prob050_kmap1_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input c\n - output out\n\nThe module should implement the circuit described by the Karnaugh map\nbelow.\n\n a\n bc 0 1\n 00 | 0 | 1 |\n 01 | 1 | 1 |\n 11 | 1 | 1 |\n 10 | 1 | 1 |\n\n", + "metadata": { + "file_size": 374, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob050_kmap1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_85", + "file": "Prob097_mux9to1v_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a (16 bits)\n - input b (16 bits)\n - input c (16 bits)\n - input d (16 bits)\n - input e (16 bits)\n - input f (16 bits)\n - input g (16 bits)\n - input h (16 bits)\n - input i (16 bits)\n - input sel ( 4 bits)\n - output out (16 bits)\n\nThe module should implement a 16-bit wide, 9-to-1 multiplexer. sel=0\nchooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set\nall output bits to '1'.\n\n", + "metadata": { + "file_size": 586, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob097_mux9to1v_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_86", + "file": "Prob130_circuit5_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a (4 bits)\n - input b (4 bits)\n - input c (4 bits)\n - input d (4 bits)\n - input e (4 bits)\n - output q (4 bits)\n\nThe module should implement a combinational circuit. Read the simulation\nwaveforms to determine what the circuit does, then implement it.\n\n time a b c d e q\n 0ns x x x x x x\n 5ns x x x x x x\n 10ns x x x x x x\n 15ns a b 0 d e b\n 20ns a b 1 d e e\n 25ns a b 2 d e a\n 30ns a b 3 d e d\n 35ns a b 4 d e f\n 40ns a b 5 d e f\n 45ns a b 6 d e f\n 50ns a b 7 d e f\n 55ns a b 8 d e f\n 60ns a b 9 d e f\n 65ns a b a d e f\n 70ns a b b d e f\n 75ns a b c d e f\n 80ns a b d d e f\n 85ns a b e d e f\n 90ns a b f d e f\n\n", + "metadata": { + "file_size": 921, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob130_circuit5_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_87", + "file": "Prob057_kmap2_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input c\n - input d\n - output out\n\nThe module should implement the circuit described by the Karnaugh map\nbelow.\n\n ab\n cd 00 01 11 10\n 00 | 1 | 1 | 0 | 1 |\n 01 | 1 | 0 | 0 | 1 |\n 11 | 0 | 1 | 1 | 1 |\n 10 | 1 | 1 | 0 | 0 |\n\n", + "metadata": { + "file_size": 432, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob057_kmap2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_88", + "file": "Prob023_vector100r_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (100 bits)\n - output out (100 bits)\n\nThe module should reverse the bit ordering of the input and write to the\noutput.\n\n", + "metadata": { + "file_size": 287, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob023_vector100r_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_89", + "file": "problems.txt", + "task_type": "spec_to_rtl", + "content": "Prob001_zero\nProb002_m2014_q4i\nProb003_step_one\nProb004_vector2\nProb005_notgate\nProb006_vectorr\nProb007_wire\nProb008_m2014_q4h\nProb009_popcount3\nProb010_mt2015_q4a\nProb011_norgate\nProb012_xnorgate\nProb013_m2014_q4e\nProb014_andgate\nProb015_vector1\nProb016_m2014_q4j\nProb017_mux2to1v\nProb018_mux256to1\nProb019_m2014_q4f\nProb020_mt2015_eq2\nProb021_mux256to1v\nProb022_mux2to1\nProb023_vector100r\nProb024_hadd\nProb025_reduction\nProb026_alwaysblock1\nProb027_fadd\nProb028_m2014_q4a\nProb029_m2014_q4g\nProb030_popcount255\nProb031_dff\nProb032_vector0\nProb033_ece241_2014_q1c\nProb034_dff8\nProb035_count1to10\nProb036_ringer\nProb037_review2015_count1k\nProb038_count15\nProb039_always_if\nProb040_count10\nProb041_dff8r\nProb042_vector4\nProb043_vector5\nProb044_vectorgates\nProb045_edgedetect2\nProb046_dff8p\nProb047_dff8ar\nProb048_m2014_q4c\nProb049_m2014_q4b\nProb050_kmap1\nProb051_gates4\nProb052_gates100\nProb053_m2014_q4d\nProb054_edgedetect\nProb055_conditional\nProb056_ece241_2013_q7\nProb057_kmap2\nProb058_alwaysblock2\nProb059_wire4\nProb060_m2014_q4k\nProb061_2014_q4a\nProb062_bugs_mux2\nProb063_review2015_shiftcount\nProb064_vector3\nProb065_7420\nProb066_edgecapture\nProb067_countslow\nProb068_countbcd\nProb069_truthtable1\nProb070_ece241_2013_q2\nProb071_always_casez\nProb072_thermostat\nProb073_dff16e\nProb074_ece241_2014_q4\nProb075_counter_2bc\nProb076_always_case\nProb077_wire_decl\nProb078_dualedge\nProb079_fsm3onehot\nProb080_timer\nProb081_7458\nProb082_lfsr32\nProb083_mt2015_q4b\nProb084_ece241_2013_q12\nProb085_shift4\nProb086_lfsr5\nProb087_gates\nProb088_ece241_2014_q5b\nProb089_ece241_2014_q5a\nProb090_circuit1\nProb091_2012_q2b\nProb092_gatesv100\nProb093_ece241_2014_q3\nProb094_gatesv\nProb095_review2015_fsmshift\nProb096_review2015_fsmseq\nProb097_mux9to1v\nProb098_circuit7\nProb099_m2014_q6c\nProb100_fsm3comb\nProb101_circuit4\nProb102_circuit3\nProb103_circuit2\nProb104_mt2015_muxdff\nProb105_rotate100\nProb106_always_nolatches\nProb107_fsm1s\nProb108_rule90\nProb109_fsm1\nProb110_fsm2\nProb111_fsm2s\nProb112_always_case2\nProb113_2012_q1g\nProb114_bugs_case\nProb115_shift18\nProb116_m2014_q3\nProb117_circuit9\nProb118_history_shift\nProb119_fsm3\nProb120_fsm3s\nProb121_2014_q3bfsm\nProb122_kmap4\nProb123_bugs_addsubz\nProb124_rule110\nProb125_kmap3\nProb126_circuit6\nProb127_lemmings1\nProb128_fsm_ps2\nProb129_ece241_2013_q8\nProb130_circuit5\nProb131_mt2015_q4\nProb132_always_if2\nProb133_2014_q3fsm\nProb134_2014_q3c\nProb135_m2014_q6b\nProb136_m2014_q6\nProb137_fsm_serial\nProb138_2012_q2fsm\nProb139_2013_q2bfsm\nProb140_fsm_hdlc\nProb141_count_clock\nProb142_lemmings2\nProb143_fsm_onehot\nProb144_conwaylife\nProb145_circuit8\nProb146_fsm_serialdata\nProb147_circuit10\nProb148_2013_q2afsm\nProb149_ece241_2013_q4\nProb150_review2015_fsmonehot\nProb151_review2015_fsm\nProb152_lemmings3\nProb153_gshare\nProb154_fsm_ps2data\nProb155_lemmings4\nProb156_review2015_fancytimer\n", + "metadata": { + "file_size": 2814, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/problems.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_90", + "file": "Prob100_fsm3comb_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in\n - input state (2 bits)\n - output next_state (2 bits)\n - output out\n\nThe module should implement the following is the state transition table\nfor a Moore state machine with one input, one output, and four states.\nUse the following state encoding: A=2'b00, B=2'b01, C=2'b10,\nD=2'b11.Implement only the state transition logic and output logic (the\ncombinational logic portion) for this state machine. Given the current\nstate (state), compute the next_state and output (out) based on the state\ntransition table.\n\n State | Next state in=0, Next state in=1 | Output\n A | A, B | 0\n B | C, B | 0\n C | A, D | 0\n D | C, B | 1\n\n", + "metadata": { + "file_size": 918, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob100_fsm3comb_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_91", + "file": "Prob122_kmap4_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input c\n - input d\n - output out\n\nThe module should implement the Karnaugh map below.\n\n ab\n cd 00 01 11 10\n 00 | 0 | 1 | 0 | 1 |\n 01 | 1 | 0 | 1 | 0 |\n 11 | 0 | 1 | 0 | 1 |\n 10 | 1 | 0 | 1 | 0 |\n\n", + "metadata": { + "file_size": 401, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob122_kmap4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_92", + "file": "Prob015_vector1_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (16 bits)\n - output out_hi ( 8 bits)\n - output out_lo ( 8 bits)\n\nThe module should implement a combinational circuit that splits an input\nhalf-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes.\n\n", + "metadata": { + "file_size": 380, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob015_vector1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_93", + "file": "Prob062_bugs_mux2_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nConsider the following implementation of an 8-bit 2-to-1 mux:\n\n module TopModule (\n input sel,\n input [7:0] a,\n input [7:0] b,\n output out\n );\n\n assign out = (~sel & a) | (sel & b);\n\n endmodule\n\nUnfortunately, this module has a bug. Implement a new version of this\nmodule that fixes the bug.\n\n", + "metadata": { + "file_size": 337, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob062_bugs_mux2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_94", + "file": "Prob114_bugs_case_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input code (8 bits)\n - output out (4 bits)\n - output valid\n\nThe module should recognize 8-bit keyboard scancodes for keys 0 through\n9. It should indicate whether one of the 10 cases were recognized\n(valid), and if so, which key was detected. If the 8-bit input is 8'h45,\n8'h16, 8'h1e, 8'h26, 8'h25, 8'h2e, 8'h36, 8'h3d, 8'h3e, or 8'h46, the\n4-bit output will be set to 0, 1, 2, 3, 4, 5, 6, 7, 8, or 9 respectively,\nthe 1-bit valid would be set to 1. If the input does not match any of the\ncases, both output signals would be set to 0.\n\n", + "metadata": { + "file_size": 695, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob114_bugs_case_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_95", + "file": "Prob090_circuit1_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - output q\n\nThe module should implement a combinational circuit. Read the simulation\nwaveforms to determine what the circuit does, then implement it.\n\n time a b q\n 0ns 0 0 0\n 5ns 0 0 0\n 10ns 0 0 0\n 15ns 0 0 0\n 20ns 0 0 0\n 25ns 0 1 0\n 30ns 0 1 0\n 35ns 1 0 0\n 40ns 1 0 0\n 45ns 1 1 1\n 50ns 1 1 1\n 55ns 0 0 0\n 60ns 0 0 0\n 65ns 0 1 0\n 70ns 0 1 0\n 75ns 1 0 0\n 80ns 1 0 0\n 85ns 1 1 1\n 90ns 1 1 1\n\n", + "metadata": { + "file_size": 651, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob090_circuit1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_96", + "file": "Prob049_m2014_q4b_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input ar\n - input d\n - output q\n\nThe module should implement a D flip flop, positive edge triggered, with\nan asynchronous reset \"ar\".\n\n", + "metadata": { + "file_size": 308, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob049_m2014_q4b_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_97", + "file": "Prob118_history_shift_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n - input predict_valid\n - input predict_taken\n - input train_mispredicted\n - input train_taken\n - input train_history (32 bits)\n - output predict_history (32 bits)\n\nThe module should implement a 32-bit global history shift register,\nincluding support for rolling back state in response to a pipeline flush\ncaused by a branch misprediction. When a branch prediction is made\n(predict_valid = 1), shift in predict_taken from the LSB side to update\nthe branch history for the predicted branch. (predict_history[0] is the\ndirection of the youngest branch.) When a branch misprediction occurs\n(train_mispredicted = 1), load the branch history register with the\nhistory after the completion of the mispredicted branch. This is the\nhistory before the mispredicted branch (train_history) concatenated with\nthe actual result of the branch (train_taken). If both a prediction and\nmisprediction occur at the same time, the misprediction takes precedence,\nbecause the pipeline flush will also flush out the branch that is\ncurrently making a prediction. predict_history is the value of the branch\nhistory register. areset is a positive edge triggered asynchronous reset\nthat resets the history counter to zero. Assume all sequential logic is\ntriggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 1466, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob118_history_shift_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_98", + "file": "Prob078_dualedge_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input d\n - output q\n\nA dual-edge triggered flip-flop is triggered on both edges of the clock.\nHowever, FPGAs don't have dual-edge triggered flip-flops, and using an\nalways @(posedge clk or negedge clk) is not accepted as a legal\nsensitivity list. Build a circuit that functionally behaves like a\ndual-edge triggered flip-flop.\n\n", + "metadata": { + "file_size": 500, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob078_dualedge_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_99", + "file": "Prob004_vector2_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (32 bits)\n - output out (32 bits)\n\nThe module should reverse the byte order of a 32-bit vector.\n\n", + "metadata": { + "file_size": 265, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob004_vector2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_100", + "file": "Prob003_step_one_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - output one\n\nThe module should always drive 1 (or logic high).\n\n", + "metadata": { + "file_size": 220, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob003_step_one_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_101", + "file": "Prob018_mux256to1_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (256 bits)\n - input sel ( 8 bits)\n - output out\n\nThe module should implement a 1-bit wide, 256-to-1 multiplexer. The 256\ninputs are all packed into a single 256-bit input vector. sel=0 should\nselect in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.\n\n", + "metadata": { + "file_size": 434, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob018_mux256to1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_102", + "file": "Prob012_xnorgate_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - output out\n\nThe module should implement an XNOR gate.\n\n", + "metadata": { + "file_size": 236, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob012_xnorgate_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_103", + "file": "Prob027_fadd_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input cin\n - output cout\n - output sum\n\nThe module should impement a full adder. A full adder adds three bits\n(including carry-in) and produces a sum and carry-out.\n\n", + "metadata": { + "file_size": 348, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob027_fadd_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_104", + "file": "Prob117_circuit9_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input a\n - output q (3 bits)\n\nThe module implements a sequential circuit. Read the simulation waveforms\nto determine what the circuit does, then implement it.\n\n time clk a q\n 0ns 0 1 x\n 5ns 1 1 4\n 10ns 0 1 4\n 15ns 1 1 4\n 20ns 0 1 4\n 25ns 1 1 4\n 30ns 0 1 4\n 35ns 1 1 4\n 40ns 0 1 4\n 45ns 1 0 4\n 50ns 0 0 4\n 55ns 1 0 5\n 60ns 0 0 5\n 65ns 1 0 6\n 70ns 0 0 6\n 75ns 1 0 0\n 80ns 0 0 0\n 85ns 1 0 1\n 90ns 0 0 1\n\n", + "metadata": { + "file_size": 693, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob117_circuit9_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_105", + "file": "Prob106_always_nolatches_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input scancode (16 bits)\n - output left\n - output down\n - output right\n - output up\n\nThe module should process scancodes from a PS/2 keyboard for a game.\nGiven the last two bytes of scancodes received, you need to indicate\nwhether one of the arrow keys on the keyboard have been pressed. This\ninvolves a fairly simple mapping, which can be implemented as a case\nstatement (or if-elseif) with four cases.\n\n Scancode[15:0] | Arrow key\n 16'he06b | left arrow\n 16'he072 | down arrow\n 16'he074 | right arrow\n 16'he075 | up arrow\n Anything else | none\n\nYour circuit has one 16-bit input, and four outputs. Build this circuit\nthat recognizes these four scancodes and asserts the correct output.\n\n", + "metadata": { + "file_size": 878, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob106_always_nolatches_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_106", + "file": "Prob153_gshare_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n\n - input predict_valid,\n - input predict_pc (7 bits)\n - output predict_taken\n - output predict_history (7 bits)\n\n - input train_valid\n - input train_taken\n - input train_mispredicted\n - input train_history (7 bits)\n - input train_pc (7 bits)\n\nThe module should implement a gshare branch predictor with 7-bit pc and\n7-bit global history, hashed (using xor) into a 7-bit index. This index\naccesses a 128-entry table of two-bit saturating counters. The branch\npredictor should contain a 7-bit global branch history register. The\nbranch predictor has two sets of interfaces: One for doing predictions\nand one for doing training. The prediction interface is used in the\nprocessor's Fetch stage to ask the branch predictor for branch direction\npredictions for the instructions being fetched. Once these branches\nproceed down the pipeline and are executed, the true outcomes of the\nbranches become known. The branch predictor is then trained using the\nactual branch direction outcomes.\n\nWhen a branch prediction is requested (predict_valid = 1) for a given pc,\nthe branch predictor produces the predicted branch direction and state of\nthe branch history register used to make the prediction. The branch\nhistory register is then updated (at the next positive clock edge) for\nthe predicted branch.\n\nWhen training for a branch is requested (train_valid = 1), the branch\npredictor is told the pc and branch history register value for the branch\nthat is being trained, as well as the actual branch outcome and whether\nthe branch was a misprediction (needing a pipeline flush). Update the\npattern history table (PHT) to train the branch predictor to predict this\nbranch more accurately next time. In addition, if the branch being\ntrained is mispredicted, also recover the branch history register to the\nstate immediately after the mispredicting branch completes execution.\n\nIf training for a misprediction and a prediction (for a different,\nyounger instruction) occurs in the same cycle, both operations will want\nto modify the branch history register. When this happens, training takes\nprecedence, because the branch being predicted will be discarded anyway.\nIf training and prediction of the same PHT entry happen at the same time,\nthe prediction sees the PHT state before training because training only\nmodifies the PHT at the next positive clock edge. The following timing\ndiagram shows the timing when training and predicting PHT entry 0 at the\nsame time. The training request at cycle 4 changes the PHT entry state in\ncycle 5, but the prediction request in cycle 4 outputs the PHT state at\ncycle 4, without considering the effect of the training request in cycle\n4. Reset is asynchronous active-high.\n\nAssume all sequential logic is triggered on the positive edge of the\nclock.\n\n", + "metadata": { + "file_size": 2965, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob153_gshare_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_107", + "file": "Prob085_shift4_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n - input load\n - input ena\n - input data (4 bits)\n - output q (4 bits)\n\nThe module should implement a 4-bit shift register (right shift), with\nasynchronous positive edge triggered areset, synchronous active high\nsignals load, and enable.\n\n (1) areset: Resets shift register to zero.\n\n (2) load: Loads shift register with data[3:0] instead of shifting.\n\n (3) ena: Shift right (q[3] becomes zero, q[0] is shifted out and\n disappears).\n\n (4) q: The contents of the shift register. If both the load and ena\n inputs are asserted (1), the load input has higher priority.\n\nAssume all sequential logic is triggered on the positive edge of the\nclock.\n\n", + "metadata": { + "file_size": 847, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob085_shift4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_108", + "file": "Prob022_mux2to1_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input sel\n - output out\n\nThe module should implement a one-bit wide, 2-to-1 multiplexer. When\nsel=0, choose a. When sel=1, choose b.\n\n", + "metadata": { + "file_size": 316, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob022_mux2to1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_109", + "file": "Prob040_count10_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - output q (4 bits)\n\nThe module should implement a decade counter that counts from 0 through\n9, inclusive, with a period of 10. Assume all sequential logic is\ntriggered on the positive edge of the clock. The reset input is active\nhigh synchronous, and should reset the counter to 0.\n\n", + "metadata": { + "file_size": 469, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob040_count10_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_110", + "file": "Prob102_circuit3_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input c\n - input d\n - output q\n\nThe module should implement a combinational circuit. Read the simulation\nwaveforms to determine what the circuit does, then implement it.\n\n time a b c d q\n 0ns 0 0 0 0 0\n 5ns 0 0 0 0 0\n 10ns 0 0 0 0 0\n 15ns 0 0 0 0 0\n 20ns 0 0 0 1 0\n 25ns 0 0 1 0 0\n 30ns 0 0 1 1 0\n 35ns 0 1 0 0 0\n 40ns 0 1 0 1 1\n 45ns 0 1 1 0 1\n 50ns 0 1 1 1 1\n 55ns 1 0 0 0 0\n 60ns 1 0 0 1 1\n 65ns 1 0 1 0 1\n 70ns 1 0 1 1 1\n 75ns 1 1 0 0 0\n 80ns 1 1 0 1 1\n 85ns 1 1 1 0 1\n 90ns 1 1 1 1 1\n\n", + "metadata": { + "file_size": 795, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob102_circuit3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_111", + "file": "Prob026_alwaysblock1_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - output out_assign\n - output out_alwaysblock\n\nThe module should implement an AND gate using both an assign statement\nand a combinational always block.\n\n", + "metadata": { + "file_size": 332, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob026_alwaysblock1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_112", + "file": "Prob121_2014_q3bfsm_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input x\n - output z\n\nThe module should implement a finite-state machine with the\nstate-assigned table shown below. Reset should synchronous active high\nreset the FSM to state 000. Assume all sequential logic is triggered on\nthe positive edge of the clock.\n\n Present state y[2:0] | Next state y[2:0] x=0, Next state y[2:0] x=1 | Output z\n 000 | 000, 001 | 0\n 001 | 001, 100 | 0\n 010 | 010, 001 | 0\n 011 | 001, 010 | 1\n 100 | 011, 100 | 1\n\n", + "metadata": { + "file_size": 632, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob121_2014_q3bfsm_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_113", + "file": "Prob092_gatesv100_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (100 bits)\n - output out_both (100 bits)\n - output out_any (100 bits)\n - output out_different (100 bits)\n\nThe module takes as input a 100-bit input vector in[99:0] and should\nproduce the following three outputs:\n\n (1) out_both: Each bit of this output vector should indicate whether\n both the corresponding input bit and its neighbour to the left are '1'.\n For example, out_both[98] should indicate if in[98] and in[99] are both\n 1. Since in[99] has no neighbour to the left, the answer is obvious so\n simply set out_both[99] to be zero.\n\n (2) out_any: Each bit of this output vector should indicate whether any\n of the corresponding input bit and its neighbour to the right are '1'.\n For example, out_any[2] should indicate if either in[2] or in[1] are 1.\n Since in[0] has no neighbour to the right, the answer is obvious so\n simply set out_any[0] to be zero.\n\n (3) out_different: Each bit of this output vector should indicate\n whether the corresponding input bit is different from its neighbour to\n the left. For example, out_different[98] should indicate if in[98] is\n different from in[99]. For this part, treat the vector as wrapping\n around, so in[99]'s neighbour to the left is in[0].\n\n", + "metadata": { + "file_size": 1398, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob092_gatesv100_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_114", + "file": "Prob032_vector0_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input vec (3 bits)\n - output outv (3 bits)\n - output o2\n - output o1\n - output o0\n\nThe module has one 3-bit input, then outputs the same vector, and also\nsplits it into three separate 1-bit outputs. Connect output o0 to the\ninput vector's position 0, o1 to position 1, etc.\n\n", + "metadata": { + "file_size": 434, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob032_vector0_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_115", + "file": "Prob138_2012_q2fsm_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input w\n - output z\n\nThe module should implement the state machine shown below:\n\n A (0) --1--> B\n A (0) --0--> A\n B (0) --1--> C\n B (0) --0--> D\n C (0) --1--> E\n C (0) --0--> D\n D (0) --1--> F\n D (0) --0--> A\n E (1) --1--> E\n E (1) --0--> D\n F (1) --1--> C\n F (1) --0--> D\n\nReset resets into state A and is synchronous active-high. Assume all\nsequential logic is triggered on the positive edge of the clock.\n\nUse separate always blocks for the state table and the state flip-flops.\nDescribe the FSM output, which is called _z_, using either continuous\nassignment statement(s) or an always block (at your discretion). Assign\nany state codes that you wish to use.\n\n", + "metadata": { + "file_size": 863, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob138_2012_q2fsm_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_116", + "file": "Prob076_always_case_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input sel (3 bits)\n - input data0 (4 bits)\n - input data1 (4 bits)\n - input data2 (4 bits)\n - input data3 (4 bits)\n - input data4 (4 bits)\n - input data5 (4 bits)\n - output out (4 bits)\n);\n\nThe module should implement a 6-to-1 multiplexer. When sel is between 0\nand 5, choose the corresponding data input. Otherwise, output 0. The data\ninputs and outputs are all 4 bits wide.\n\n", + "metadata": { + "file_size": 545, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob076_always_case_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_117", + "file": "Prob053_m2014_q4d_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input in\n - output out\n\nThe module should implement the following circuit: A D flip-flop takes as\ninput the output of a two-input XOR. The flip-flop is positive edge\ntriggered by clk, but there is no reset. The XOR takes as input 'in'\nalong with the output 'out' of the flip-flop.\n\n", + "metadata": { + "file_size": 454, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob053_m2014_q4d_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_118", + "file": "Prob063_review2015_shiftcount_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input shift_ena\n - input count_ena\n - input data\n - output q (4 bits)\n\nThe module should implement a four-bit shift register that also acts as a\ndown counter. Data is shifted in most-significant-bit first when\nshift_ena is 1. The number currently in the shift register is decremented\nwhen count_ena is 1. Since the full system doesn't ever use shift_ena and\ncount_ena together, it does not matter what your circuit does if both\ncontrol inputs are 1 (this mainly means that it doesn't matter which case\ngets higher priority). Assume all sequential logic is triggered on the\npositive edge of the clock.\n\n", + "metadata": { + "file_size": 776, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob063_review2015_shiftcount_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_119", + "file": "Prob036_ringer_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input ring\n - input vibrate_mode\n - output ringer\n - output motor\n\nThe module should implement a circuit to control a cellphone's ringer and\nvibration motor. Whenever the phone needs to ring from an incoming call\n(input ring), your circuit must either turn on the ringer (output ringer\n= 1) or the motor (output motor = 1), but not both. If the phone is in\nvibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn\non the ringer.\n\n", + "metadata": { + "file_size": 606, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob036_ringer_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_120", + "file": "Prob093_ece241_2014_q3_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input c\n - input d\n - output mux_in (4 bits)\n\nFor the following Karnaugh map, give the circuit implementation using one\n4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using\nas few as possible. You are not allowed to use any other logic gate and\nyou must use _a_ and _b_ as the multiplexer selector inputs, as shown on\nthe 4-to-1 multiplexer below.\n\n ab\n cd 00 01 11 10\n 00 | 0 | 0 | 0 | 1 |\n 01 | 1 | 0 | 0 | 0 |\n 11 | 1 | 0 | 1 | 1 |\n 10 | 1 | 0 | 0 | 1 |\n\nConsider a block diagram with inputs 'c' and 'd' going into a module\ncalled \"TopModule\". This \"TopModule\" has four outputs, mux_in[3:0], that\nconnect to a four input mux. The mux takes as input {a,b} and ab = 00 is\nconnected to mux_in[0], ab=01 is connected to mux_in[1], and so in. You\nare implementing in Verilog just the portion labelled \"TopModule\", such\nthat the entire circuit (including the 4-to-1 mux) implements the K-map.\n\n", + "metadata": { + "file_size": 1085, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob093_ece241_2014_q3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_121", + "file": "Prob146_fsm_serialdata_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input in\n - input reset\n - output out_byte (8 bits)\n - output done\n\nIn many (older) serial communications protocols, each data byte is sent\nalong with a start bit and a stop bit, to help the receiver delimit bytes\nfrom the stream of bits. One common scheme is to use one start bit (0), 8\ndata bits, and 1 stop bit (1). The line is also at logic 1 when nothing\nis being transmitted (idle). Design a finite state machine that will\nidentify when bytes have been correctly received when given a stream of\nbits. It needs to identify the start bit, wait for all 8 data bits, then\nverify that the stop bit was correct. The module will also output the\ncorrectly-received data byte. `out_byte` needs to be valid when `done` is\n1, and is don't-care otherwise. If the stop bit does not appear when\nexpected, the FSM must wait until it finds a stop bit before attempting\nto receive the next byte. Include a active-high synchronous reset. Note\nthat the serial protocol sends the least significant bit first. It should\nassert done each time it finds a stop bit. Assume all sequential logic is\ntriggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 1298, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob146_fsm_serialdata_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_122", + "file": "Prob054_edgedetect_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input in (8 bits)\n - output pedge (8 bits)\n\nThe module should examine each bit in an 8-bit vector and detect when the\ninput signal changes from 0 in one clock cycle to 1 the next (similar to\npositive edge detection). The output bit should be set the cycle after a\n0 to 1 transition occurs.\n\n", + "metadata": { + "file_size": 466, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob054_edgedetect_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_123", + "file": "Prob019_m2014_q4f_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in1\n - input in2\n - output out\n\nThe module should implement the following circuit in Verilog. Two inputs\n(in1 and in2) go to an AND gate, but the in2 input to the AND gate has a\nbubble. The output of the AND gate is connected to 'out'.\n\n", + "metadata": { + "file_size": 402, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob019_m2014_q4f_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_124", + "file": "Prob101_circuit4_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input c\n - input d\n - output q\n\nThe module should implement a combinational circuit. Read the simulation\nwaveforms to determine what the circuit does, then implement it.\n\n time a b c d q\n 0ns 0 0 0 0 0\n 5ns 0 0 0 0 0\n 10ns 0 0 0 0 0\n 15ns 0 0 0 0 0\n 20ns 0 0 0 1 0\n 25ns 0 0 1 0 1\n 30ns 0 0 1 1 1\n 35ns 0 1 0 0 1\n 40ns 0 1 0 1 1\n 45ns 0 1 1 0 1\n 50ns 0 1 1 1 1\n 55ns 1 0 0 0 0\n 60ns 1 0 0 1 0\n 65ns 1 0 1 0 1\n 70ns 1 0 1 1 1\n 75ns 1 1 0 0 1\n 80ns 1 1 0 1 1\n 85ns 1 1 1 0 1\n 90ns 1 1 1 1 1\n\n", + "metadata": { + "file_size": 795, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob101_circuit4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_125", + "file": "Prob109_fsm1_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n - input in\n - output out\n\nThe module should implement a Moore machine with the diagram described\nbelow:\n\n B (1) --0--> A\n B (1) --1--> B\n A (0) --0--> B\n A (0) --1--> A\n\nIt should asynchronously reset into state B if reset if high.\n\n", + "metadata": { + "file_size": 424, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob109_fsm1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_126", + "file": "Prob111_fsm2s_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input j\n - input k\n - output out\n\nThe module should implement a Moore state machine with two states, two\ninputs, and one output according to diagram described below. Reset is an\nactive-high synchronous reset to state OFF.\n\n OFF (out=0) --j=0--> OFF\n OFF (out=0) --j=1--> ON\n ON (out=1) --k=0--> ON\n ON (out=1) --k=1--> OFF\n\n", + "metadata": { + "file_size": 519, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob111_fsm2s_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_127", + "file": "Prob119_fsm3_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n - input in\n - output out\n\nThe module should implement a Moore state machine with the following\nstate transition table with one input, one output, and four states.\nImplement this state machine. Include a positive edge triggered\nasynchronous reset that resets the FSM to state A. Assume all sequential\nlogic is triggered on the positive edge of the clock.\n\n state | next state in=0, next state in=1 | output\n A | A, B | 0\n B | C, B | 0\n C | A, D | 0\n D | C, B | 1\n\n", + "metadata": { + "file_size": 783, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob119_fsm3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_128", + "file": "Prob029_m2014_q4g_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in1\n - input in2\n - input in3\n - output out\n\nThe module should impement the following circuit: A two-input XNOR\n(connected to 'in1' and 'in2) has an output connected to the input of a\ntwo-input XOR. The second input of the XOR is 'in3.' The output of the\nXOR is 'out'.\n\n", + "metadata": { + "file_size": 436, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob029_m2014_q4g_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_129", + "file": "Prob137_fsm_serial_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input in\n - output done\n\nIn many (older) serial communications protocols, each data byte is sent\nalong with a start bit and a stop bit, to help the receiver delimit bytes\nfrom the stream of bits. One common scheme is to use one start bit (0), 8\ndata bits, and 1 stop bit (1). The line is also at logic 1 when nothing\nis being transmitted (idle).\n\nImplement a finite state machine that will identify when bytes have been\ncorrectly received when given a stream of bits. It needs to identify the\nstart bit, wait for all 8 data bits, then verify that the stop bit was\ncorrect. If the stop bit does not appear when expected, the FSM must wait\nuntil it finds a stop bit before attempting to receive the next byte.\nInclude a active-high synchronous reset. Note that the serial protocol\nsends the least significant bit first.\n\nAssume all sequential logic is triggered on the positive edge of the\nclock.\n\n", + "metadata": { + "file_size": 1084, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob137_fsm_serial_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_130", + "file": "Prob060_m2014_q4k_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input resetn\n - input in\n - output out\n\nThe module should implement a shift register with four D flops. Assume\nall sequential logic is triggered on the positive edge of the clock.\nReset is active-low synchronous resettable.\n\n", + "metadata": { + "file_size": 398, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob060_m2014_q4k_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_131", + "file": "Prob039_always_if_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input sel_b1\n - input sel_b2\n - output out_assign\n - output out_always\n\nThe module should implement a 2-to-1 mux that chooses between a and b.\nChoose b if both sel_b1 and sel_b2 are true. Otherwise, choose a. Do the\nsame twice, once using assign statements and once using a procedural if\nstatement.\n\n", + "metadata": { + "file_size": 483, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob039_always_if_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_132", + "file": "Prob142_lemmings2_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n - input bump_left\n - input bump_right\n - input ground\n - output walk_left\n - output walk_right\n - output aaah\n\nThe game Lemmings involves critters with fairly simple brains. So simple\nthat we are going to model it using a finite state machine. In the\nLemmings' 2D world, Lemmings can be in one of two states: walking left\n(walk_left is 1) or walking right (walk_right is 1). It will switch\ndirections if it hits an obstacle. In particular, if a Lemming is bumped\non the left (by receiving a 1 on bump_left), it will walk right. If it's\nbumped on the right (by receiving a 1 on bump_right), it will walk left.\nIf it's bumped on both sides at the same time, it will still switch\ndirections.\n\nIn addition to walking left and right and changing direction when bumped,\nwhen ground=0, the Lemming will fall and say \"aaah!\". When the ground\nreappears (ground=1), the Lemming will resume walking in the same\ndirection as before the fall. Being bumped while falling does not affect\nthe walking direction, and being bumped in the same cycle as ground\ndisappears (but not yet falling), or when the ground reappears while\nstill falling, also does not affect the walking direction.\n\nImplement a Moore state machine that models this behaviour. areset is\npositive edge triggered asynchronous reseting the Lemming machine to walk\nleft. Assume all sequential logic is triggered on the positive edge of\nthe clock.\n\n", + "metadata": { + "file_size": 1586, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob142_lemmings2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_133", + "file": "Prob041_dff8r_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input d (8 bits)\n - output q (8 bits)\n\nThe module should include 8 D flip-flops with active high synchronous\nreset setting the output to zero. All DFFs should be triggered by the\npositive edge of clk.\n\n", + "metadata": { + "file_size": 390, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob041_dff8r_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_134", + "file": "Prob105_rotate100_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input load\n - input ena ( 2 bits)\n - input data (100 bits)\n - output q (100 bits)\n\nThe module should implement a 100-bit left/right rotator, with\nsynchronous load and left/right enable. A rotator shifts-in the\nshifted-out bit from the other end of the register, unlike a shifter that\ndiscards the shifted-out bit and shifts in a zero. If enabled, a rotator\nrotates the bits around and does not modify/discard them.\n\n (1) load: Loads shift register with data[99:0] instead of rotating.\n Synchronous active high.\n\n (2) ena[1:0]: Synchronous. Chooses whether and which direction to\n rotate:\n (a) 2'b01 rotates right by one bit,\n (b) 2'b10 rotates left by one bit,\n (c) 2'b00 and 2'b11 do not rotate.\n\n (3) q: The contents of the rotator.\n\n", + "metadata": { + "file_size": 943, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob105_rotate100_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_135", + "file": "Prob150_review2015_fsmonehot_prompt.txt", + "task_type": "spec_to_rtl", + "content": "I would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input d\n - input done_counting\n - input ack\n - input state (10 bits)\n - output B3_next\n - output S_next\n - output S1_next\n - output Count_next\n - output Wait_next\n - output done\n - output counting\n - output shift_ena\n\nThe module should implement the following Moore state machine with 3\ninput (d, done_counting, ack) and 3 outputs (shift_ena, counting, done).\nUnless otherwise stated in the diagram below, assume outputs are 0 and\ninputs are don't cares.\n\nstate (output) --input--> next state\n-------------------------------------------\n S () --d=0--> S\n S () --d=1--> S1\n S1 () --d=0--> S\n S1 () --d=1--> S11\n S11 () --d=0--> S110\n S11 () --d=1--> S11\n S110 () --d=0--> S\n S110 () --d=1--> B0\n B0 (shift_ena=1) --(always go to next cycle)--> B1\n B1 (shift_ena=1) --(always go to next cycle)--> B2\n B2 (shift_ena=1) --(always go to next cycle)--> B3\n B3 (shift_ena=1) --(always go to next cycle)--> Count\n Count (counting=1) --done_counting=0--> Count\n Count (counting=1) --done_counting=1--> Wait\n Wait (done=1) --ack=0--> Wait\n Wait (done=1) --ack=1--> S\n\nAt reset, the state machine starts in state \"S\". Derive next-state logic\nequations and output logic equations by inspection assuming the following\none-hot encoding is used: (S, S1, S11, S110, B0, B1, B2, B3, Count, Wait)\n= (10'b0000000001, 10'b0000000010, 10'b0000000100, ... , 10'b1000000000)\n\nDerive state transition and output logic equations by inspection assuming\na one-hot encoding. Implement only the state transition logic and output\nlogic (the combinational logic portion) for this state machine.\n\nWrite code that generates the following signals:\n\n - B3_next -- Assert when next-state is B3 state\n - S_next -- Assert when next-state is S state\n - S1_next -- Assert when next-state is S1 state\n - Count_next -- Assert when next-state is Count state\n - Wait_next -- Assert when next-state is Wait state\n - done -- output logic\n - counting -- output logic\n - shift_ena -- output logic\n\n", + "metadata": { + "file_size": 2267, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob150_review2015_fsmonehot_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_136", + "file": "Prob154_fsm_ps2data_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input in (8 bits)\n - output out_bytes (24 bits)\n - output done\n\nThe module should implement a finite state machine that will search for\nmessage boundaries when given an input byte stream. The algorithm we'll\nuse is to discard bytes until we see one with in[3]=1. We then assume\nthat this is byte 1 of a message, and signal the receipt of a message\nonce all 3 bytes have been received (done). The FSM should signal done in\nthe cycle immediately after the third byte of each message was\nsuccessfully received.\n\nImplement the datapath module that will output the 24-bit (3 byte)\nmessage whenever a packet is received (out_bytes[23:16] is the first\nbyte, out_bytes[15:8] is the second byte, etc.). The reset signal is\nactive high synchronous. out_bytes needs to be valid whenever the done\nsignal is asserted. You may output anything at other times (i.e.,\ndon't-care). Assume all sequential logic is triggered on the positive\nedge of the clock.\n\nHere is an example waveform:\n\n time clk rst in done out_bytes\n 0ns 0 1 0 x x\n 5ns 1 1 0 0 x\n 10ns 0 1 0 0 x\n 15ns 1 0 2c 0 x\n 20ns 0 0 2c 0 x\n 25ns 1 0 81 0 x\n 30ns 0 0 81 0 x\n 35ns 1 0 9 0 x\n 40ns 0 0 9 0 x\n 45ns 1 0 6b 1 2c8109\n 50ns 0 0 6b 1 2c8109\n 55ns 1 0 d 0 x\n 60ns 0 0 d 0 x\n 65ns 1 0 8d 0 x\n 70ns 0 0 8d 0 x\n 75ns 1 0 6d 1 6b0d8d\n 80ns 0 0 6d 1 6b0d8d\n 85ns 1 0 12 0 x\n 90ns 0 0 12 0 x\n 95ns 1 0 1 0 x\n 100ns 0 0 1 0 x\n 105ns 1 0 d 1 6d1201\n 110ns 0 0 d 1 6d1201\n 115ns 1 0 76 0 x\n 120ns 0 0 76 0 x\n 125ns 1 0 3d 0 x\n 130ns 0 0 3d 0 x\n 135ns 1 0 ed 1 d763d\n 140ns 0 0 ed 1 d763d\n 145ns 1 0 8c 0 x\n 150ns 0 0 8c 0 x\n 155ns 1 0 f9 0 x\n 160ns 0 0 f9 0 x\n 165ns 1 0 ce 1 ed8cf9\n 170ns 0 0 ce 1 ed8cf9\n 175ns 1 0 c5 0 x\n 180ns 0 0 c5 0 x\n 185ns 1 0 aa 0 x\n 190ns 0 0 aa 0 x\n\n", + "metadata": { + "file_size": 2483, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob154_fsm_ps2data_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_137", + "file": "Prob096_review2015_fsmseq_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input data\n - output start_shifting\n\nThe module should implement a finite-state machine that searches for the\nsequence 1101 in an input bit stream. When the sequence is found, it\nshould set start_shifting to 1, forever, until reset. Reset is active\nhigh synchronous. Assume all sequential logic is triggered on the\npositive edge of the clock.\n\n", + "metadata": { + "file_size": 532, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob096_review2015_fsmseq_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_138", + "file": "Prob132_always_if2_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nConsider the following adder-subtractor with a zero flag:\n\n module TopModule (\n input cpu_overheated,\n output reg shut_off_computer,\n input arrived,\n input gas_tank_empty,\n output reg keep_driving\n );\n\n always @(*) begin\n if (cpu_overheated)\n shut_off_computer = 1;\n end\n\n always @(*) begin\n if (~arrived)\n keep_driving = ~gas_tank_empty;\n end\n\n endmodule\n\nUnfortunately, this module has a bug. Implement a new version of this\nmodule that fixes the bug.\n\n", + "metadata": { + "file_size": 561, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob132_always_if2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_139", + "file": "Prob038_count15_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - output q (4 bits)\n\nThe module should implement a 4-bit binary counter that counts from 0\nthrough 15, inclusive, with a period of 16. Assume all sequential logic\nis triggered on the positive edge of the clock. The reset input is active\nhigh synchronous, and should reset the counter to 0.\n\n", + "metadata": { + "file_size": 476, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob038_count15_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_140", + "file": "Prob011_norgate_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - output out\n\nThe module should implement a NOR gate.\n\n", + "metadata": { + "file_size": 234, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob011_norgate_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_141", + "file": "Prob020_mt2015_eq2_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input A (2 bits)\n - input B (2 bits)\n - output z\n\nThe module should implement a circuit that has two 2-bit inputs A[1:0]\nand B[1:0], and produces an output z. The value of z should be 1 if A =\nB, otherwise z should be 0.\n\n", + "metadata": { + "file_size": 381, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob020_mt2015_eq2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_142", + "file": "Prob059_wire4_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input a\n - input b\n - input c\n - output w\n - output x\n - output y\n - output z\n\nThe module should behave like wires that makes these connections:\n\n a -> w\n b -> x\n b -> y\n c -> z\n\n", + "metadata": { + "file_size": 343, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob059_wire4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_143", + "file": "Prob134_2014_q3c_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input x\n - input y (3 bits)\n - output Y0\n - output z\n\nThe module should implement the output logic and next state logic for an\nFSM using the table shown below. Note that the output Y0 is Y[0] of the\nnext state signal.\n\n Present state input y[2:0] | Next state Y[2:0] when x=0, Next state Y[2:0] when x=1 | Output z\n 000 | 000, 001 | 0\n 001 | 001, 100 | 0\n 010 | 010, 001 | 0\n 011 | 001, 010 | 1\n 100 | 011, 100 | 1\n\n", + "metadata": { + "file_size": 601, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob134_2014_q3c_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_144", + "file": "Prob061_2014_q4a_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input w\n - input R\n - input E\n - input L\n - output Q\n\nThe module will be one stage in a larger n-bit shift register circuit.\nInput E is for enabling shift, R for value to load, L is asserted when it\nshould load, and w is the input from the prevous stage of the shift\nregister. Assume all sequential logic is triggered on the positive edge\nof the clock.\n\n", + "metadata": { + "file_size": 529, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob061_2014_q4a_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_145", + "file": "Prob152_lemmings3_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n - input bump_left\n - input bump_right\n - input ground\n - input dig\n - output walk_left\n - output walk_right\n - output aaah\n - output digging\n\nThe game Lemmings involves critters with fairly simple brains. So simple\nthat we are going to model it using a finite state machine. In the\nLemmings' 2D world, Lemmings can be in one of two states: walking left\n(walk_left is 1) or walking right (walk_right is 1). It will switch\ndirections if it hits an obstacle. In particular, if a Lemming is bumped\non the left (by receiving a 1 on bump_left), it will walk right. If it's\nbumped on the right (by receiving a 1 on bump_right), it will walk left.\nIf it's bumped on both sides at the same time, it will still switch\ndirections.\n\nIn addition to walking left and right and changing direction when bumped,\nwhen ground=0, the Lemming will fall and say \"aaah!\". When the ground\nreappears (ground=1), the Lemming will resume walking in the same\ndirection as before the fall. Being bumped while falling does not affect\nthe walking direction, and being bumped in the same cycle as ground\ndisappears (but not yet falling), or when the ground reappears while\nstill falling, also does not affect the walking direction.\n\nIn addition to walking and falling, Lemmings can sometimes be told to do\nuseful things, like dig (it starts digging when dig=1). A Lemming can dig\nif it is currently walking on ground (ground=1 and not falling), and will\ncontinue digging until it reaches the other side (ground=0). At that\npoint, since there is no ground, it will fall (aaah!), then continue\nwalking in its original direction once it hits ground again. As with\nfalling, being bumped while digging has no effect, and being told to dig\nwhen falling or when there is no ground is ignored. (In other words, a\nwalking Lemming can fall, dig, or switch directions. If more than one of\nthese conditions are satisfied, fall has higher precedence than dig,\nwhich has higher precedence than switching directions.)\n\nImplement a Moore state machine that models this behaviour. areset is\npositive edge triggered asynchronous reseting the Lemming machine to walk\nleft. Assume all sequential logic is triggered on the positive edge of\nthe clock.\n\n\n", + "metadata": { + "file_size": 2390, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob152_lemmings3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_146", + "file": "Prob115_shift18_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input load\n - input ena\n - input amount (2 bits)\n - input data (64 bits)\n - output q (64 bits)\n\nThe module should implement a 64-bit arithmetic shift register, with\nsynchronous load. The shifter can shift both left and right, and by 1 or\n8 bit positions, selected by \"amount.\" Assume the right shit is an\narithmetic right shift.\n\nSignals are defined as below:\n\n (1) load: Loads shift register with data[63:0] instead of shifting.\n Active high.\n (2) ena: Chooses whether to shift. Active high.\n (3) amount: Chooses which direction and how much to shift.\n (a) 2'b00: shift left by 1 bit.\n (b) 2'b01: shift left by 8 bits.\n (c) 2'b10: shift right by 1 bit.\n (d) 2'b11: shift right by 8 bits.\n (4) q: The contents of the shifter.\n\n", + "metadata": { + "file_size": 932, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob115_shift18_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_147", + "file": "Prob072_thermostat_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input mode\n - input too_cold\n - input too_hot\n - input fan_on\n - output heater\n - output aircon\n - output fan\n\nThe module should implement a heating/cooling thermostat controller which\ncontrols both a heater (during winter) and an air conditioner (during\nsummer). The module should on and off the heater, air conditioning, and\nblower fan as appropriate. The thermostat can be in one of two modes:\nheating (mode = 1) and cooling (mode = 0). In heating mode, turn the\nheater on when it is too cold (too_cold = 1) but do not use the air\nconditioner. In cooling mode, turn the air conditioner on when it is too\nhot (too_hot = 1), but do not turn on the heater. When the heater or air\nconditioner are on, also turn on the fan to circulate the air. In\naddition, the user can also request the fan to turn on (fan_on = 1), even\nif the heater and air conditioner are off.\n\n", + "metadata": { + "file_size": 1025, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob072_thermostat_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_148", + "file": "Prob089_ece241_2014_q5a_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input areset\n - input x\n - output z\n\nThe module should implement a one-input one-output serial 2's\ncomplementer Moore state machine. The input (x) is a series of bits (one\nper clock cycle) beginning with the least-significant bit of the number,\nand the output (Z) is the 2's complement of the input. The machine will\naccept input numbers of arbitrary length. The circuit requires a positive\nedge triggered asynchronous reset. The conversion begins when Reset is\nreleased and stops when Reset is asserted. Assume all sequential logic is\ntriggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 755, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob089_ece241_2014_q5a_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_149", + "file": "Prob149_ece241_2013_q4_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input s (3 bits)\n - output fr2\n - output fr1\n - output fr0\n - output dfr\n\nA large reservior of water serves several users. In order to keep the\nlevel of water succificently high, three sensors are placed vertically at\n5-inch intervals. When the water level is above the highest sensor s[2],\nthe input flow rate should be zero. When the level is below the lowest\nsensor s[0], the flow rate should be at maximum (both Nominal flow valve\nand Supplemental flow valve opened). The flow rate when the level is\nbetween the upper and lower sensors is determined by two factors: the\nwater level and the level previous to the last sensor change. Each water\nlevel has a nominal flow rate associated with it as show in the table\nbelow. If the sensor change indicates that the previous level was lower\nthan the current level, the flow rate should be increased by opening the\nSupplemental flow valve (controlled by dfr).\n\n Water Level | Sensors Asserted | Nominal Flow Rate Inputs to be Asserted\n Above s[2] | s[0], s[1], s[2] | None\n Between s[2] and s[1] | s[0], s[1] | fr0\n Between s[1] and s[0] | s[0] | fr0, fr1\n Below s[0] | None | fr0, fr1, fr2\n\nAlso include an active-high synchronous reset that resets the state\nmachine to a state equivalent to if the water level had been low for a\nlong time (no sensors asserted, and all four outputs asserted).\n\n", + "metadata": { + "file_size": 1598, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob149_ece241_2013_q4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_150", + "file": "Prob068_countbcd_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - output ena (3 bits)\n - output q (16 bits)\n\nThe module should implement a 4-digit BCD (binary-coded decimal) counter.\nEach decimal digit is encoded using 4 bits: q[3:0] is the ones digit,\nq[7:4] is the tens digit, etc. For digits [3:1], also output an enable\nsignal indicating when each of the upper three digits should be\nincremented. Include a synchronous active-high reset. Assume all\nsequential logic is triggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 642, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob068_countbcd_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_151", + "file": "Prob136_m2014_q6_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input w\n - output z\n\nThe module should implement the state machine shown below:\n\n A (0) --0--> B\n A (0) --1--> A\n B (0) --0--> C\n B (0) --1--> D\n C (0) --0--> E\n C (0) --1--> D\n D (0) --0--> F\n D (0) --1--> A\n E (1) --0--> E\n E (1) --1--> D\n F (1) --0--> C\n F (1) --1--> D\n\nAssume all sequential logic is triggered on the positive edge of the\nclock.\n\n", + "metadata": { + "file_size": 551, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob136_m2014_q6_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_152", + "file": "Prob008_m2014_q4h_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in\n - output out\n\nThe module should assign the output port to the same value as the input\nport combinationally.\n\n", + "metadata": { + "file_size": 277, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob008_m2014_q4h_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_153", + "file": "Prob123_bugs_addsubz_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nConsider the following adder-subtractor with a zero flag:\n\n synthesis verilog_input_version verilog_2001\n module TopModule (\n input do_sub,\n input [7:0] a,\n input [7:0] b,\n output reg [7:0] out,\n output reg result_is_zero\n );\n\n always @(*) begin\n case (do_sub)\n 0: out = a+b;\n 1: out = a-b;\n endcase\n\n if (~out)\n result_is_zero = 1;\n end\n\n endmodule\n\nUnfortunately, this module has a bug. Implement a new version of this\nmodule that fixes the bug.\n\n", + "metadata": { + "file_size": 551, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob123_bugs_addsubz_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_154", + "file": "Prob067_countslow_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input slowena\n - output q (4 bits)\n\nThe module should implement a decade counter that counts from 0 through\n9, inclusive, with a period of 10. The reset input is active high\nsynchronous, and should reset the counter to 0. We want to be able to\npause the counter rather than always incrementing every clock cycle, so\nthe \"slowena\" input if high indicates when the counter should increment.\nAssume all sequential logic is triggered on the positive edge of the\nclock.\n\n", + "metadata": { + "file_size": 654, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob067_countslow_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_155", + "file": "Prob094_gatesv_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (4 bits)\n - output out_both (4 bits)\n - output out_any (4 bits)\n - output out_different (4 bits)\n\nYou are given a four-bit input vector. We want to know some relationships\nbetween each bit and its neighbour:\n\n (1) out_both: Each bit of this output vector should indicate whether\n both the corresponding input bit and its neighbour to the left (higher\n index) are '1'. For example, out_both[2] should indicate if in[2] and\n in[3] are both 1. Since in[3] has no neighbour to the left, the answer\n is obvious so we don't need to know out_both[3].\n\n (2) out_any: Each bit of this output vector should indicate whether any\n of the corresponding input bit and its neighbour to the right are '1'.\n For example, out_any[2] should indicate if either in[2] or in[1] are 1.\n Since in[0] has no neighbour to the right, the answer is obvious so we\n don't need to know out_any[0].\n\n (3) out_different: Each bit of this output vector should indicate\n whether the corresponding input bit is different from its neighbour to\n the left. For example, out_different[2] should indicate if in[2] is\n different from in[3]. For this part, treat the vector as wrapping\n around, so in[3]'s neighbour to the left is in[0].\n\n", + "metadata": { + "file_size": 1400, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob094_gatesv_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_156", + "file": "Prob025_reduction_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input in (8 bits)\n - output parity\n\nParity checking is often used as a simple method of detecting errors when\ntransmitting data through an imperfect channel. The module should compute\na parity bit for an 8-bit byte (which will add a 9th bit to the byte). We\nwill use \"even\" parity, where the parity bit is just the XOR of all 8\ndata bits.\n\n", + "metadata": { + "file_size": 502, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob025_reduction_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_spec-to-rtl", + "id": "veval_157", + "file": "Prob066_edgecapture_prompt.txt", + "task_type": "spec_to_rtl", + "content": "\nI would like you to implement a module named TopModule with the following\ninterface. All input and output ports are one bit unless otherwise\nspecified.\n\n - input clk\n - input reset\n - input in (32 bits)\n - output out (32 bits)\n\nThe module should examine each bit in the 32-bit input vector, and\ncapture when the input signal changes from 1 in one clock cycle to 0 the\nnext. \"Capture\" means that the output will remain 1 until the register is\nreset (active high synchronous reset). Assume all sequential logic is\ntriggered on the positive edge of the clock.\n\n", + "metadata": { + "file_size": 567, + "file_path": "datasets/verilog_eval_v2/dataset_spec-to-rtl/Prob066_edgecapture_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_158", + "file": "Prob087_gates_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n output out_and,\n output out_or,\n output out_xor,\n output out_nand,\n output out_nor,\n output out_xnor,\n output out_anotb\n);\n", + "metadata": { + "file_size": 173, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob087_gates_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_159", + "file": "Prob084_ece241_2013_q12_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input enable,\n input S,\n input A,\n input B,\n input C,\n output reg Z\n);\n", + "metadata": { + "file_size": 111, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob084_ece241_2013_q12_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_160", + "file": "Prob009_popcount3_prompt.txt", + "task_type": "code_completion", + "content": "\nA \"population count\" circuit counts the number of '1's in an input\nvector. Build a population count circuit for a 3-bit input vector.\n\nmodule TopModule (\n input [2:0] in,\n output [1:0] out\n);\n\n", + "metadata": { + "file_size": 196, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob009_popcount3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_161", + "file": "Prob037_review2015_count1k_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a counter that counts from 0 to 999, inclusive, with a period of\n1000 cycles. The reset input is active high synchronous, and should reset\nthe counter to 0.\n\nmodule TopModule (\n input clk,\n input reset,\n output reg [9:0] q\n);\n\n", + "metadata": { + "file_size": 237, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob037_review2015_count1k_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_162", + "file": "Prob064_vector3_prompt.txt", + "task_type": "code_completion", + "content": "\nGiven several input vectors, concatenate them together then split them up\ninto several output vectors. There are six 5-bit input vectors: a, b, c,\nd, e, and f, for a total of 30 bits of input. There are four 8-bit output\nvectors: w, x, y, and z, for 32 bits of output. The output should be a\nconcatenation of the input vectors followed by two 1 bits (the two 1 bits\nshould be in the LSB positions).\n\nmodule TopModule (\n input [4:0] a,\n input [4:0] b,\n input [4:0] c,\n input [4:0] d,\n input [4:0] e,\n input [4:0] f,\n output [7:0] w,\n output [7:0] x,\n output [7:0] y,\n output [7:0] z\n);\n\n", + "metadata": { + "file_size": 597, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob064_vector3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_163", + "file": "Prob047_dff8ar_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate 8 D flip-flops with active high asynchronous reset. The output\nshould be reset to 0. All DFFs should be triggered by the positive edge\nof clk.\n\nmodule TopModule (\n input clk,\n input [7:0] d,\n input areset,\n output reg [7:0] q\n);\n\n", + "metadata": { + "file_size": 242, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob047_dff8ar_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_164", + "file": "Prob129_ece241_2013_q8_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input aresetn,\n input x,\n output reg z\n);\n", + "metadata": { + "file_size": 79, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob129_ece241_2013_q8_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_165", + "file": "Prob131_mt2015_q4_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input x,\n input y,\n output z\n);\n", + "metadata": { + "file_size": 56, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob131_mt2015_q4_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_166", + "file": "Prob035_count1to10_prompt.txt", + "task_type": "code_completion", + "content": "\nMake a decade counter that counts 1 through 10, inclusive. The reset\ninput is active high synchronous, and should reset the counter to 1.\n\nmodule TopModule (\n input clk,\n input reset,\n output reg [3:0] q\n);\n\n", + "metadata": { + "file_size": 212, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob035_count1to10_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_167", + "file": "Prob137_fsm_serial_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input in,\n input reset,\n output done\n);\n", + "metadata": { + "file_size": 77, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob137_fsm_serial_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_168", + "file": "Prob125_kmap3_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement the circuit described by the Karnaugh map below. d is\ndon't-care, which means you may choose to output whatever value is\nconvenient.\n\n ab\n cd 01 00 10 11\n 00 | d | 0 | 1 | 1 |\n 01 | 0 | 0 | d | d |\n 11 | 0 | 1 | 1 | 1 |\n 10 | 0 | 1 | 1 | 1 |\n\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output reg out\n);\n\n", + "metadata": { + "file_size": 366, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob125_kmap3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_169", + "file": "Prob126_circuit6_prompt.txt", + "task_type": "code_completion", + "content": "\nThis is a combinational circuit. Read the simulation waveforms to\ndetermine what the circuit does, then implement it.\n\n time a q\n 0ns x x\n 5ns x x\n 10ns x x\n 15ns 0 1232\n 20ns 1 aee0\n 25ns 2 27d4\n 30ns 3 5a0e\n 35ns 4 2066\n 40ns 5 64ce\n 45ns 6 c526\n 50ns 7 2f19\n 55ns 0 1232\n 60ns 1 aee0\n 65ns 2 27d4\n 70ns 4 2066\n 75ns 1 aee0\n 80ns 1 aee0\n 85ns 3 5a0e\n 90ns 5 64ce\n\nmodule TopModule (\n input [2:0] a,\n output reg [15:0] q\n);\n\n", + "metadata": { + "file_size": 503, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob126_circuit6_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_170", + "file": "Prob052_gates100_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a combinational circuit with 100 inputs, in[99:0]. There are 3\noutputs:\n\n (1) out_and: output of a 100-input AND gate.\n (2) out_or: output of a 100-input OR gate.\n (3) out_xor: output of a 100-input XOR gate.\n\nmodule TopModule (\n input [99:0] in,\n output out_and,\n output out_or,\n output out_xor\n);\n\n", + "metadata": { + "file_size": 314, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob052_gates100_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_171", + "file": "Prob149_ece241_2013_q4_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n input [3:1] s,\n output reg fr3,\n output reg fr2,\n output reg fr1,\n output reg dfr\n);\n", + "metadata": { + "file_size": 139, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob149_ece241_2013_q4_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_172", + "file": "Prob008_m2014_q4h_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input in,\n output out\n);\n", + "metadata": { + "file_size": 48, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob008_m2014_q4h_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_173", + "file": "Prob004_vector2_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [31:0] in,\n output [31:0] out\n);\n", + "metadata": { + "file_size": 62, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob004_vector2_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_174", + "file": "Prob007_wire_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a module with one input and one output that behaves like a wire.\n\nmodule TopModule (\n input in,\n output out\n);\n\n", + "metadata": { + "file_size": 122, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob007_wire_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_175", + "file": "Prob113_2012_q1g_prompt.txt", + "task_type": "code_completion", + "content": "\nConsider the function f shown in the Karnaugh map below. Implement this\nfunction.\n\n x[1]x[2]x[3]x[4]\n 00 01 11 10\n 00 | 1 | 0 | 0 | 1 |\n 01 | 0 | 0 | 0 | 0 |\n 11 | 1 | 1 | 1 | 0 |\n 10 | 1 | 1 | 0 | 1 |\n\nmodule TopModule (\n input [4:1] x,\n output logic f\n);\n\n", + "metadata": { + "file_size": 278, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob113_2012_q1g_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_176", + "file": "Prob140_fsm_hdlc_prompt.txt", + "task_type": "code_completion", + "content": "\nSynchronous HDLC framing involves decoding a continuous bit stream of\ndata to look for bit patterns that indicate the beginning and end of\nframes (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a\n\"flag\" that indicate frame boundaries. To avoid the data stream from\naccidentally containing \"flags\", the sender inserts a zero after every 5\nconsecutive 1s which the receiver must detect and discard. We also need\nto signal an error if there are 7 or more consecutive 1s. Create a\nMoore-type finite state machine to recognize these three sequences:\n\n (1) 0111110: Signal a bit needs to be discarded (disc).\n (2) 01111110: Flag the beginning/end of a frame (flag).\n (3) 01111111...: Error (7 or more 1s) (err).\n\nWhen the FSM is reset, it should be in a state that behaves as though the\nprevious input were 0. The reset signal is active high synchronous. The\noutput signals should be asserted for a complete cycle beginning on the\nclock cycle after the condition occurs.\n\nmodule TopModule (\n input clk,\n input reset,\n input in,\n output disc,\n output flag,\n output err\n);\n\n", + "metadata": { + "file_size": 1091, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob140_fsm_hdlc_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_177", + "file": "Prob135_m2014_q6b_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [3:1] y,\n input w,\n output reg Y2\n);\n", + "metadata": { + "file_size": 67, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob135_m2014_q6b_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_178", + "file": "Prob034_dff8_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate 8 D flip-flops. All DFFs should be triggered by the positive edge\nof clk.\n\nmodule TopModule (\n input clk,\n input [7:0] d,\n output reg [7:0] q\n);\n\n", + "metadata": { + "file_size": 157, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob034_dff8_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_179", + "file": "Prob035_count1to10_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n output reg [3:0] q\n);\n", + "metadata": { + "file_size": 72, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob035_count1to10_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_180", + "file": "Prob145_circuit8_prompt.txt", + "task_type": "code_completion", + "content": "\nThis is a sequential circuit. Read the simulation waveforms to determine\nwhat the circuit does, then implement it.\n\n time clock a p q\n 0ns 0 0 x x\n 5ns 0 0 x x\n 10ns 0 0 x x\n 15ns 0 0 x x\n 20ns 0 0 x x\n 25ns 1 0 0 x\n 30ns 1 0 0 x\n 35ns 1 0 0 x\n 40ns 1 0 0 x\n 45ns 1 0 0 x\n 50ns 1 0 0 x\n 55ns 0 0 0 0\n 60ns 0 0 0 0\n 65ns 0 0 0 0\n 70ns 0 1 0 0\n 75ns 0 0 0 0\n 80ns 0 1 0 0\n 85ns 1 0 0 0\n 90ns 1 1 1 0\n 95ns 1 0 0 0\n 100ns 1 1 1 0\n 105ns 1 0 0 0\n 110ns 1 1 1 0\n 115ns 0 0 1 1\n 120ns 0 1 1 1\n 125ns 0 0 1 1\n 130ns 0 1 1 1\n 135ns 0 0 1 1\n 140ns 0 0 1 1\n 145ns 1 0 0 1\n 150ns 1 0 0 1\n 155ns 1 0 0 1\n 160ns 1 0 0 1\n 165ns 1 1 1 1\n 170ns 1 0 0 1\n 175ns 0 1 0 0\n 180ns 0 0 0 0\n 185ns 0 1 0 0\n 190ns 0 0 0 0\n\nmodule TopModule (\n input clock,\n input a,\n output reg p,\n output reg q\n);\n\n", + "metadata": { + "file_size": 1238, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob145_circuit8_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_181", + "file": "Prob152_lemmings3_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input areset,\n input bump_left,\n input bump_right,\n input ground,\n input dig,\n output walk_left,\n output walk_right,\n output aaah,\n output digging\n);\n", + "metadata": { + "file_size": 193, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob152_lemmings3_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_182", + "file": "Prob131_mt2015_q4_prompt.txt", + "task_type": "code_completion", + "content": "\nModule A implements the boolean function z = (x^y) & x.\n\nModule B can be described by the following simulation waveform:\n\n time x y z\n 0ns 0 0 1\n 5ns 0 0 1\n 10ns 0 0 1\n 15ns 0 0 1\n 20ns 0 0 1\n 25ns 1 0 0\n 30ns 1 0 0\n 35ns 0 1 0\n 40ns 0 1 0\n 45ns 1 1 1\n 50ns 1 1 1\n 55ns 0 0 1\n 60ns 0 1 0\n 65ns 0 1 0\n 70ns 1 1 1\n 75ns 0 1 0\n 80ns 0 1 0\n 85ns 0 1 0\n 90ns 1 0 0\n\nNow consider a top-level that uses two A submodules and two B submodules.\nThe first input of all four submodules is connect to input 'x', and the\nsecond input of all four submodules is connected to 'y'. The output of\nthe first A submodule is connected to a two-input OR, along with the\noutput of the first B submodule. The second pair of A and B submodules is\nsimilarly connected to an AND gate. The output of the OR and the AND is\nconnected to an XOR, whose output is 'z'.\n\nImplement this circuit in Verilog.\n\nmodule TopModule (\n input x,\n input y,\n output z\n);\n\n", + "metadata": { + "file_size": 1011, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob131_mt2015_q4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_183", + "file": "Prob081_7458_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input p1a,\n input p1b,\n input p1c,\n input p1d,\n input p1e,\n input p1f,\n output p1y,\n input p2a,\n input p2b,\n input p2c,\n input p2d,\n output p2y\n);\n", + "metadata": { + "file_size": 180, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob081_7458_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_184", + "file": "Prob091_2012_q2b_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [5:0] y,\n input w,\n output Y1,\n output Y3\n);\n", + "metadata": { + "file_size": 76, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob091_2012_q2b_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_185", + "file": "Prob033_ece241_2014_q1c_prompt.txt", + "task_type": "code_completion", + "content": "\nAssume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0].\nThese numbers are added to produce s[7:0]. Also compute whether a\n(signed) overflow has occurred.\n\nmodule TopModule (\n input [7:0] a,\n input [7:0] b,\n output [7:0] s,\n output overflow\n);\n\n", + "metadata": { + "file_size": 267, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob033_ece241_2014_q1c_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_186", + "file": "Prob098_circuit7_prompt.txt", + "task_type": "code_completion", + "content": "\nThis is a sequential circuit. Read the simulation waveforms to determine\nwhat the circuit does, then implement it.\n\n time clk a q\n 0ns 0 x x\n 5ns 1 0 x\n 10ns 0 0 x\n 15ns 1 0 1\n 20ns 0 0 1\n 25ns 1 0 1\n 30ns 0 0 1\n 35ns 1 1 1\n 40ns 0 1 1\n 45ns 1 1 0\n 50ns 0 1 0\n 55ns 1 1 0\n 60ns 0 1 0\n 65ns 1 1 0\n 70ns 0 1 0\n 75ns 1 1 0\n 80ns 0 1 0\n 85ns 1 1 0\n 90ns 0 1 0\n\nmodule TopModule (\n input clk,\n input a,\n output reg q\n);\n\n", + "metadata": { + "file_size": 540, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob098_circuit7_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_187", + "file": "Prob077_wire_decl_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output out,\n output out_n\n);\n", + "metadata": { + "file_size": 96, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob077_wire_decl_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_188", + "file": "Prob014_andgate_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n output out\n);\n", + "metadata": { + "file_size": 58, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob014_andgate_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_189", + "file": "Prob075_counter_2bc_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a two-bit saturating counter. The counter increments (up to a\nmaximum of 3) when train_valid = 1 and train_taken = 1. It decrements\n(down to a minimum of 0) when train_valid = 1 and train_taken = 0. When\nnot training (train_valid = 0), the counter keeps its value unchanged.\nareset is a positive edge triggered asynchronous reset that resets the\ncounter to weakly not-taken (2'b01). Output state[1:0] is the two-bit\ncounter value.\n\nmodule TopModule (\n input clk,\n input areset,\n input train_valid,\n input train_taken,\n output logic [1:0] state\n);\n\n", + "metadata": { + "file_size": 560, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob075_counter_2bc_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_190", + "file": "Prob056_ece241_2013_q7_prompt.txt", + "task_type": "code_completion", + "content": "\nA JK flip-flop has the below truth table. Note: Qold is the output of the\nflip-flop before the positive clock edge.\n\n J | K | Q\n 0 | 0 | Qold\n 0 | 1 | 0\n 1 | 0 | 1\n 1 | 1 | ~Qold\n\nmodule TopModule (\n input clk,\n input j,\n input k,\n output reg Q\n);\n\n", + "metadata": { + "file_size": 259, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob056_ece241_2013_q7_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_191", + "file": "Prob151_review2015_fsm_prompt.txt", + "task_type": "code_completion", + "content": "\nWe want to create a timer that:\n\n (1) is started when a particular pattern (1101) is detected,\n (2) shifts in 4 more bits to determine the duration to delay,\n (3) waits for the counters to finish counting, and\n (4) notifies the user and waits for the user to acknowledge the timer.\n\nIn this problem, implement just the finite-state machine that controls\nthe timer. The data path (counters and some comparators) are not included\nhere.\n\nThe serial data is available on the data input pin. When the pattern 1101\nis received, the state machine must then assert output shift_ena for\nexactly 4 clock cycles. After that, the state machine asserts its\ncounting output to indicate it is waiting for the counters, and waits\nuntil input done_counting is high.At that point, the state machine must\nassert done to notify the user the timer has timed out, and waits until\ninput ack is 1 before being reset to look for the next occurrence of the\nstart sequence (1101). The state machine should have a active high\nsynchronous reset, setting the state to where it begins searching for the\ninput sequence 1101.\n\nmodule TopModule (\n input clk,\n input reset,\n input data,\n output reg shift_ena,\n output reg counting,\n input done_counting,\n output reg done,\n input ack\n);\n\n", + "metadata": { + "file_size": 1265, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob151_review2015_fsm_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_192", + "file": "Prob017_mux2to1v_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [99:0] a,\n input [99:0] b,\n input sel,\n output [99:0] out\n);\n", + "metadata": { + "file_size": 92, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob017_mux2to1v_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_193", + "file": "Prob097_mux9to1v_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [15:0] a,\n input [15:0] b,\n input [15:0] c,\n input [15:0] d,\n input [15:0] e,\n input [15:0] f,\n input [15:0] g,\n input [15:0] h,\n input [15:0] i,\n input [3:0] sel,\n output logic [15:0] out\n);\n", + "metadata": { + "file_size": 230, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob097_mux9to1v_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_194", + "file": "Prob124_rule110_prompt.txt", + "task_type": "code_completion", + "content": "\nRule 110 is a one-dimensional cellular automaton with interesting\nproperties (such as being Turing-complete). There is a one-dimensional\narray of cells (on or off). At each time step, the state of each cell\nchanges. In Rule 110, the next state of each cell depends only on itself\nand its two neighbours, according to the following table:\n\n Left[i+1] | Center[i] | Right[i-1] | Center's next state \n 1 | 1 | 1 | 0\n 1 | 1 | 0 | 1\n 1 | 0 | 1 | 1\n 1 | 0 | 0 | 0\n 0 | 1 | 1 | 1\n 0 | 1 | 0 | 1\n 0 | 0 | 1 | 1\n 0 | 0 | 0 | 0\n\nIn this circuit, create a 512-cell system (q[511:0]), and advance by one\ntime step each clock cycle. The synchronous active high load input\nindicates the state of the system should be loaded with data[511:0].\nAssume the boundaries (q[-1] and q[512], if they existed) are both zero (off).\n\nmodule TopModule (\n input clk,\n input load,\n input [511:0] data,\n output reg [511:0] q\n);\n\n", + "metadata": { + "file_size": 1113, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob124_rule110_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_195", + "file": "Prob133_2014_q3fsm_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n input s,\n input w,\n output reg z\n);\n", + "metadata": { + "file_size": 88, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob133_2014_q3fsm_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_196", + "file": "Prob057_kmap2_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output out\n);\n", + "metadata": { + "file_size": 80, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob057_kmap2_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_197", + "file": "Prob087_gates_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a combinational circuit with two inputs, a and b. There are 7\noutputs, each with a logic gate driving it:\n\n (1) out_and: a and b\n (2) out_or: a or b\n (3) out_xor: a xor b\n (4) out_nand: a nand b\n (5) out_nor: a nor b\n (6) out_xnor: a xnor b\n (7) out_anotb: a and-not b\n\nmodule TopModule (\n input a,\n input b,\n output out_and,\n output out_or,\n output out_xor,\n output out_nand,\n output out_nor,\n output out_xnor,\n output out_anotb\n);\n\n", + "metadata": { + "file_size": 457, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob087_gates_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_198", + "file": "Prob065_7420_prompt.txt", + "task_type": "code_completion", + "content": "\nThe 7400-series integrated circuits are a series of digital chips with a\nfew gates each. The 7420 is a chip with two 4-input NAND gates.\n\nCreate a module with the same functionality as the 7420 chip. It has 8\ninputs and 2 outputs.\n\nmodule TopModule (\n input p1a,\n input p1b,\n input p1c,\n input p1d,\n output p1y,\n input p2a,\n input p2b,\n input p2c,\n input p2d,\n output p2y\n);\n\n", + "metadata": { + "file_size": 387, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob065_7420_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_199", + "file": "Prob138_2012_q2fsm_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n input w,\n output z\n);\n", + "metadata": { + "file_size": 73, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob138_2012_q2fsm_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_200", + "file": "Prob053_m2014_q4d_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input in,\n output logic out\n);\n", + "metadata": { + "file_size": 67, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob053_m2014_q4d_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_201", + "file": "Prob084_ece241_2013_q12_prompt.txt", + "task_type": "code_completion", + "content": "\nIn this question, you will design a circuit for an 8x1 memory, where\nwriting to the memory is accomplished by shifting-in bits, and reading is\n\"random access\", as in a typical RAM. You will then use the circuit to\nrealize a 3-input logic function. First, create an 8-bit shift register\nwith 8 D-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7].\nThe shift register input should be called S, which feeds the input of\nQ[0] (MSB is shifted in first). The enable input is synchronous active\nhigh and controls whether to shift. Extend the circuit to have 3\nadditional inputs A,B,C and an output Z. The circuit's behaviour should\nbe as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so\non. Your circuit should contain ONLY the 8-bit shift register, and\nmultiplexers.\n\nmodule TopModule (\n input clk,\n input enable,\n input S,\n input A,\n input B,\n input C,\n output reg Z\n);\n\n", + "metadata": { + "file_size": 902, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob084_ece241_2013_q12_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_202", + "file": "Prob069_truthtable1_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input x3,\n input x2,\n input x1,\n output f\n);\n", + "metadata": { + "file_size": 70, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob069_truthtable1_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_203", + "file": "Prob042_vector4_prompt.txt", + "task_type": "code_completion", + "content": "\nOne common place to see a replication operator is when sign-extending a\nsmaller number to a larger one, while preserving its signed value. This\nis done by replicating the sign bit (the most significant bit) of the\nsmaller number to the left. For example, sign-extending 4'b0101 (5) to 8\nbits results in 8'b00000101 (5), while sign-extending 4'b1101 (-3) to 8\nbits results in 8'b11111101 (-3). Build a circuit that sign-extends an\n8-bit number to 32 bits. This requires a concatenation of 24 copies of\nthe sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit\nnumber itself.\n\nmodule TopModule (\n input [7:0] in,\n output [31:0] out\n);\n\n", + "metadata": { + "file_size": 648, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob042_vector4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_204", + "file": "Prob103_circuit2_prompt.txt", + "task_type": "code_completion", + "content": "\nThis is a combinational circuit. Read the simulation waveforms to\ndetermine what the circuit does, then implement it.\n\n time a b c d q\n 0ns 0 0 0 0 1\n 5ns 0 0 0 0 1\n 10ns 0 0 0 0 1\n 15ns 0 0 0 0 1\n 20ns 0 0 0 1 0\n 25ns 0 0 1 0 0\n 30ns 0 0 1 1 1\n 35ns 0 1 0 0 0\n 40ns 0 1 0 1 1\n 45ns 0 1 1 0 1\n 50ns 0 1 1 1 0\n 55ns 1 0 0 0 0\n 60ns 1 0 0 1 1\n 65ns 1 0 1 0 1\n 70ns 1 0 1 1 0\n 75ns 1 1 0 0 1\n 80ns 1 1 0 1 0\n 85ns 1 1 1 0 0\n 90ns 1 1 1 1 1\n\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output q\n);\n\n", + "metadata": { + "file_size": 639, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob103_circuit2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_205", + "file": "Prob129_ece241_2013_q8_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement a Mealy-type finite state machine that recognizes the sequence\n\"101\" on an input signal named x. Your FSM should have an output signal,\nz, that is asserted to logic-1 when the \"101\" sequence is detected. Your\nFSM should also have a negative edge triggered asynchronous reset. You\nmay only have 3 states in your state machine. Your FSM should recognize\noverlapping sequences.\n\nmodule TopModule (\n input clk,\n input aresetn,\n input x,\n output reg z\n);\n\n", + "metadata": { + "file_size": 466, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob129_ece241_2013_q8_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_206", + "file": "Prob016_m2014_q4j_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [3:0] x,\n input [3:0] y,\n output [4:0] sum\n);\n", + "metadata": { + "file_size": 76, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob016_m2014_q4j_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_207", + "file": "Prob133_2014_q3fsm_prompt.txt", + "task_type": "code_completion", + "content": "\nConsider a finite state machine with inputs s and w. Assume that the FSM\nbegins in a reset state called A, as depicted below. The FSM remains in\nstate A as long as s = 0, and it moves to state B when s = 1. Once in\nstate B the FSM examines the value of the input w in the next three clock\ncycles. If w = 1 in exactly two of these clock cycles, then the FSM has\nto set an output z to 1 in the following clock cycle. Otherwise z has to\nbe 0. The FSM continues checking w for the next three clock cycles, and\nso on. Use as few states as possible. Note that the s input is used only\nin state A, so you need to consider just the w input. Assume reset is\nactive high synchronous.\n\nmodule TopModule (\n input clk,\n input reset,\n input s,\n input w,\n output reg z\n);\n\n", + "metadata": { + "file_size": 764, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob133_2014_q3fsm_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_208", + "file": "Prob070_ece241_2013_q2_prompt.txt", + "task_type": "code_completion", + "content": "\nA single-output digital system with four inputs (a,b,c,d) generates a\nlogic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1,\n4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers\n3, 8, 11, and 12 never occur in this system. For example, 7 corresponds\nto a,b,c,d being set to 0,1,1,1, respectively. Determine the output\nout_sop in minimum sum-of-products form, and the output out_pos in\nminimum product-of-sums form.\n\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output out_sop,\n output out_pos\n);\n\n", + "metadata": { + "file_size": 556, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob070_ece241_2013_q2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_209", + "file": "Prob082_lfsr32_prompt.txt", + "task_type": "code_completion", + "content": "\nA linear feedback shift register is a shift register usually with a few\nXOR gates to produce the next state of the shift register. A Galois LFSR\nis one particular arrangement that shifts right, where a bit position with\na \"tap\" is XORed with the LSB output bit (q[0]) to produce its next value,\nwhile bit positions without a tap shift right unchanged. Build a 32-bit Galois\nLFSR with taps at bit positions 32, 22, 2, and 1. Reset should be active high\nsynchronous, and should reset the output q to 32'h1.\n\nmodule TopModule (\n input clk,\n input reset,\n output reg [31:0] q\n);\n\n", + "metadata": { + "file_size": 581, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob082_lfsr32_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_210", + "file": "Prob046_dff8p_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input [7:0] d,\n input reset,\n output reg [7:0] q\n);\n", + "metadata": { + "file_size": 89, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob046_dff8p_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_211", + "file": "Prob122_kmap4_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output reg out\n);\n", + "metadata": { + "file_size": 84, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob122_kmap4_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_212", + "file": "Prob071_always_casez_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a priority encoder for 8-bit inputs. Given an 8-bit vector, the\noutput should report the first (least significant) bit in the vector that\nis 1. Report zero if the input vector has no bits that are high. For\nexample, the input 8'b10010000 should output 3'd4, because bit[4] is\nfirst bit that is high.\n\nmodule TopModule (\n input [7:0] in,\n output reg [2:0] pos\n);\n\n", + "metadata": { + "file_size": 372, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob071_always_casez_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_213", + "file": "Prob090_circuit1_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n output q\n);\n", + "metadata": { + "file_size": 56, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob090_circuit1_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_214", + "file": "Prob135_m2014_q6b_prompt.txt", + "task_type": "code_completion", + "content": "\nConsider the state machine shown below:\n\n A (0) --0--> B\n A (0) --1--> A\n B (0) --0--> C\n B (0) --1--> D\n C (0) --0--> E\n C (0) --1--> D\n D (0) --0--> F\n D (0) --1--> A\n E (1) --0--> E\n E (1) --1--> D\n F (1) --0--> C\n F (1) --1--> D\n\nAssume that you want to Implement the FSM using three flip-flops and\nstate codes y[3:1] = 000, 001, ..., 101 for states A, B, ..., F,\nrespectively. Implement just the next-state logic for y[2] in Verilog.\nThe output Y2 is y[2].\n\nmodule TopModule (\n input [3:1] y,\n input w,\n output reg Y2\n);\n\n", + "metadata": { + "file_size": 543, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob135_m2014_q6b_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_215", + "file": "Prob132_always_if2_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input cpu_overheated,\n output reg shut_off_computer,\n input arrived,\n input gas_tank_empty,\n output reg keep_driving\n);\n", + "metadata": { + "file_size": 146, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob132_always_if2_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_216", + "file": "Prob001_zero_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a circuit that always outputs a LOW.\n\nmodule TopModule (\n output zero\n);\n\n", + "metadata": { + "file_size": 82, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob001_zero_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_217", + "file": "Prob076_always_case_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [2:0] sel,\n input [3:0] data0,\n input [3:0] data1,\n input [3:0] data2,\n input [3:0] data3,\n input [3:0] data4,\n input [3:0] data5,\n output reg [3:0] out\n);\n", + "metadata": { + "file_size": 191, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob076_always_case_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_218", + "file": "Prob099_m2014_q6c_prompt.txt", + "task_type": "code_completion", + "content": "\nConsider the state machine shown below:\n\n A (0) --0--> B\n A (0) --1--> A\n B (0) --0--> C\n B (0) --1--> D\n C (0) --0--> E\n C (0) --1--> D\n D (0) --0--> F\n D (0) --1--> A\n E (1) --0--> E\n E (1) --1--> D\n F (1) --0--> C\n F (1) --1--> D\n\nResets into state A. For this part, assume that a one-hot code is used\nwith the state assignment y[6:1] = 000001, 000010, 000100, 001000,\n010000, 100000 for states A, B,..., F, respectively.\n\nWrite Verilog for the next-state signals Y2 and Y4 corresponding to\nsignal y[2] and y[4]. Derive the logic equations by inspection assuming a\none-hot encoding.\n\nmodule TopModule (\n input [6:1] y,\n input w,\n output Y2,\n output Y4\n);\n\n", + "metadata": { + "file_size": 676, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob099_m2014_q6c_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_219", + "file": "Prob054_edgedetect_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input [7:0] in,\n output reg [7:0] pedge\n);\n", + "metadata": { + "file_size": 79, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob054_edgedetect_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_220", + "file": "Prob083_mt2015_q4b_prompt.txt", + "task_type": "code_completion", + "content": "\nThe module can be described by the following simulation waveform:\n\n time x y z\n 0ns 0 0 1\n 5ns 0 0 1\n 10ns 0 0 1\n 15ns 0 0 1\n 20ns 0 0 1\n 25ns 1 0 0\n 30ns 1 0 0\n 35ns 0 1 0\n 40ns 0 1 0\n 45ns 1 1 1\n 50ns 1 1 1\n 55ns 0 0 1\n 60ns 0 1 0\n 65ns 0 1 0\n 70ns 1 1 1\n 75ns 0 1 0\n 80ns 0 1 0\n 85ns 0 1 0\n 90ns 1 0 0\n\nmodule TopModule (\n input x,\n input y,\n output z\n);\n\n", + "metadata": { + "file_size": 445, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob083_mt2015_q4b_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_221", + "file": "Prob059_wire4_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input c,\n output w,\n output x,\n output y,\n output z\n);\n", + "metadata": { + "file_size": 103, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob059_wire4_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_222", + "file": "Prob069_truthtable1_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a combinational circuit that implements the truth table.\n\n x3 | x2 | x1 | f\n 0 | 0 | 0 | 0\n 0 | 0 | 1 | 0\n 0 | 1 | 0 | 1\n 0 | 1 | 1 | 1\n 1 | 0 | 0 | 0\n 1 | 0 | 1 | 1\n 1 | 1 | 0 | 0\n 1 | 1 | 1 | 1\n\nmodule TopModule (\n input x3,\n input x2,\n input x1,\n output f\n);\n\n", + "metadata": { + "file_size": 308, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob069_truthtable1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_223", + "file": "Prob139_2013_q2bfsm_prompt.txt", + "task_type": "code_completion", + "content": "\nConsider a finite state machine that is used to control some type of\nmotor. The FSM has inputs x and y, which come from the motor, and\nproduces outputs f and g, which control the motor. There is also a clock\ninput called clk and a reset input (synchronous, active low) called\nresetn. The FSM has to work as follows. As long as the reset input is\nasserted, the FSM stays in a beginning state, called state A. When the\nreset signal is de-asserted, then after the next clock edge the FSM has\nto set the output f to 1 for one clock cycle. Then, the FSM has to\nmonitor the x input. When x has produced the values 1, 0, 1 in three\nsuccessive clock cycles, then g should be set to 1 on the following clock\ncycle. While maintaining g = 1 the FSM has to monitor the y input. If y\nhas the value 1 within at most two clock cycles, then the FSM should\nmaintain g = 1 permanently (that is, until reset). But if y does not\nbecome 1 within two clock cycles, then the FSM should set g = 0\npermanently (until reset).\n\nmodule TopModule (\n input clk,\n input resetn,\n input x,\n input y,\n output f,\n output g\n);\n\n", + "metadata": { + "file_size": 1099, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob139_2013_q2bfsm_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_224", + "file": "Prob012_xnorgate_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n output out\n);\n", + "metadata": { + "file_size": 58, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob012_xnorgate_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_225", + "file": "Prob080_timer_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement a timer that counts down for a given number of clock cycles,\nthen asserts a signal to indicate that the given duration has elapsed. A\ngood way to implement this is with a down-counter that asserts an output\nsignal when the count becomes 0. At each clock cycle:\n\n (1) If load = 1, load the internal counter with the 10-bit data, the\n number of clock cycles the timer should count before timing out. The\n counter can be loaded at any time, including when it is still counting\n and has not yet reached 0.\n\n (2) If load = 0, the internal counter should decrement by 1. The output\n signal tc (\"terminal count\") indicates whether the internal counter has\n reached 0. Once the internal counter has reached 0, it should stay 0\n (stop counting) until the counter is loaded again.\n\nmodule TopModule (\n input clk,\n input load,\n input [9:0] data,\n output tc\n);\n\n", + "metadata": { + "file_size": 873, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob080_timer_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_226", + "file": "Prob104_mt2015_muxdff_prompt.txt", + "task_type": "code_completion", + "content": "\nConsider this Verilog module \"full_module\":\n\n module full_module (\n input [2:0] r, // load value\n input L, // load\n input clk, // clock\n output reg [2:0] q // output\n\n always @(posedge clk) begin\n if (L) begin\n q <= r;\n end else begin\n q <= {q[1] ^ q[2], q[0], q[2]};\n end\n end\n\n endmodule\n\nNote that q[2:0] is three bits wide, representing three flip-flops that can be\nloaded from r when L is asserted. You want to factor full_module into a hierarchical\ndesign, flipflop and 2:1 multiplexer are in a submodule \"TopModule\", and that submodule\nwill be instantiated three times in full_module code. Create the submodule called \"TopModule\".\nYou do not have to provide the revised full_module.\n\nmodule TopModule (\n input clk,\n input L,\n input q_in,\n input r_in,\n output reg Q\n);\n\n", + "metadata": { + "file_size": 837, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob104_mt2015_muxdff_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_227", + "file": "Prob123_bugs_addsubz_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input do_sub,\n input [7:0] a,\n input [7:0] b,\n output reg [7:0] out,\n output reg result_is_zero\n);\n", + "metadata": { + "file_size": 125, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob123_bugs_addsubz_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_228", + "file": "Prob107_fsm1s_prompt.txt", + "task_type": "code_completion", + "content": "\nThis is a Moore state machine with two states, one input, and one output.\nImplement this state machine in Verilog. The reset state is B and reset\nis active-high synchronous.\n\n B (out=1) --in=0--> A\n B (out=1) --in=1--> B\n A (out=0) --in=0--> B\n A (out=0) --in=1--> A\n\nmodule TopModule (\n input clk,\n input in,\n input reset,\n output out\n);\n\n", + "metadata": { + "file_size": 349, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob107_fsm1s_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_229", + "file": "Prob006_vectorr_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [7:0] in,\n output [7:0] out\n);\n", + "metadata": { + "file_size": 60, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob006_vectorr_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_230", + "file": "Prob110_fsm2_prompt.txt", + "task_type": "code_completion", + "content": "\nThis is a Moore state machine with two states, two inputs, and one\noutput. Implement this state machine in Verilog. Reset is an active-high\nasynchronous reset to state OFF.\n\n OFF (out=0) --j=0--> OFF\n OFF (out=0) --j=1--> ON\n ON (out=1) --k=0--> ON\n ON (out=1) --k=1--> OFF\n\nmodule TopModule (\n input clk,\n input j,\n input k,\n input areset,\n output out\n);\n\n", + "metadata": { + "file_size": 369, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob110_fsm2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_231", + "file": "Prob155_lemmings4_prompt.txt", + "task_type": "code_completion", + "content": "\nThe game Lemmings involves critters with fairly simple brains. So simple\nthat we are going to model it using a finite state machine. In the\nLemmings' 2D world, Lemmings can be in one of two states: walking left\n(walk_left is 1) or walking right (walk_right is 1). It will switch\ndirections if it hits an obstacle. In particular, if a Lemming is bumped\non the left (by receiving a 1 on bump_left), it will walk right. If it's\nbumped on the right (by receiving a 1 on bump_right), it will walk left.\nIf it's bumped on both sides at the same time, it will still switch\ndirections.\n\nIn addition to walking left and right and changing direction when bumped,\nwhen ground=0, the Lemming will fall and say \"\"aaah!\"\". When the ground\nreappears (ground=1), the Lemming will resume walking in the same\ndirection as before the fall. Being bumped while falling does not affect\nthe walking direction, and being bumped in the same cycle as ground\ndisappears (but not yet falling), or when the ground reappears while\nstill falling, also does not affect the walking direction.\n\nIn addition to walking and falling, Lemmings can sometimes be told to do\nuseful things, like dig (it starts digging when dig=1). A Lemming can dig\nif it is currently walking on ground (ground=1 and not falling), and will\ncontinue digging until it reaches the other side (ground=0). At that\npoint, since there is no ground, it will fall (aaah!), then continue\nwalking in its original direction once it hits ground again. As with\nfalling, being bumped while digging has no effect, and being told to dig\nwhen falling or when there is no ground is ignored. (In other words, a\nwalking Lemming can fall, dig, or switch directions. If more than one of\nthese conditions are satisfied, fall has higher precedence than dig,\nwhich has higher precedence than switching directions.)\n\nAlthough Lemmings can walk, fall, and dig, Lemmings aren't invulnerable.\nIf a Lemming falls for too long then hits the ground, it can splatter. In\nparticular, if a Lemming falls for more than 20 clock cycles then hits\nthe ground, it will splatter and cease walking, falling, or digging (all\n4 outputs become 0), forever (Or until the FSM gets reset). There is no\nupper limit on how far a Lemming can fall before hitting the ground.\nLemmings only splatter when hitting the ground; they do not splatter in\nmid-air.\n\nImplement a Moore state machine that models this behaviour. areset is\npositive edge triggered asynchronous reseting the Lemming machine to walk\nleft.\n\nmodule TopModule (\n input clk,\n input areset,\n input bump_left,\n input bump_right,\n input ground,\n input dig,\n output walk_left,\n output walk_right,\n output aaah,\n output digging\n);\n\n", + "metadata": { + "file_size": 2691, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob155_lemmings4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_232", + "file": "Prob033_ece241_2014_q1c_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [7:0] a,\n input [7:0] b,\n output [7:0] s,\n output overflow\n);\n", + "metadata": { + "file_size": 93, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob033_ece241_2014_q1c_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_233", + "file": "Prob139_2013_q2bfsm_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input resetn,\n input x,\n input y,\n output f,\n output g\n);\n", + "metadata": { + "file_size": 97, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob139_2013_q2bfsm_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_234", + "file": "Prob013_m2014_q4e_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement a 2-input NOR gate.\n\nmodule TopModule (\n input in1,\n input in2,\n output logic out\n);\n\n", + "metadata": { + "file_size": 100, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob013_m2014_q4e_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_235", + "file": "Prob107_fsm1s_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input in,\n input reset,\n output out\n);\n", + "metadata": { + "file_size": 76, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob107_fsm1s_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_236", + "file": "Prob148_2013_q2afsm_prompt.txt", + "task_type": "code_completion", + "content": "\nConsider the FSM described by the state diagram shown below:\n\n A --r1=0,r2=0,r3=0--> A\n A --r1=1--> B\n A --r1=0,r2=1--> C\n A --r1=0,r2=0,r3=0--> D\n B (g1=1) --r1=1--> B\n B (g1=1) --r1=0--> A\n C (g2=1) --r2=1--> C\n C (g2=1) --r2=0--> A\n\nResetn is an active-low synchronous reset that resets into state A. This\nFSM acts as an arbiter circuit, which controls access to some type of\nresource by three requesting devices. Each device makes its request for\nthe resource by setting a signal _r[i]_ = 1, where _r[i]_ is either\n_r[1]_, _r[2]_, or _r[3]_. Each r[i] is an input signal to the FSM, and\nrepresents one of the three devices. The FSM stays in state _A_ as long\nas there are no requests. When one or more request occurs, then the FSM\ndecides which device receives a grant to use the resource and changes to\na state that sets that device's _g[i]_ signal to 1. Each _g[i]_ is an\noutput from the FSM. There is a priority system, in that device 1 has a\nhigher priority than device 2, and device 3 has the lowest priority.\nHence, for example, device 3 will only receive a grant if it is the only\ndevice making a request when the FSM is in state _A_. Once a device, _i_,\nis given a grant by the FSM, that device continues to receive the grant\nas long as its request, _r[i]_ = 1.\n\nWrite complete Verilog code that represents this FSM. Use separate always\nblocks for the state table and the state flip-flops, as done in lectures.\nDescribe the FSM outputs, _g[i]_, using either continuous assignment\nstatement(s) or an always block (at your discretion). Assign any state\ncodes that you wish to use.\n\nmodule TopModule (\n input clk,\n input resetn,\n input [3:1] r,\n output [3:1] g\n);\n\n", + "metadata": { + "file_size": 1687, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob148_2013_q2afsm_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_237", + "file": "Prob077_wire_decl_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement the following circuit. Create two intermediate wires (named\nanything you want) to connect the AND and OR gates together. Note that\nthe wire that feeds the NOT gate is really wire `out`, so you do not\nnecessarily need to declare a third wire here. Notice how wires are\ndriven by exactly one source (output of a gate), but can feed multiple\ninputs.\n\nThe circuit is composed of two layers. The first layer, counting from the\ninput, is two AND gates: one whose input is connected to a and b, and the\nsecond is connected to c and d. The second layer there is an OR gate to\nOR the two AND outputs, connected the output 'out'. Additionally, there\nis an inverted output 'out_n'.\n\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output out,\n output out_n\n);\n\n", + "metadata": { + "file_size": 779, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob077_wire_decl_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_238", + "file": "Prob081_7458_prompt.txt", + "task_type": "code_completion", + "content": "\nThe 7458 is a chip with four AND gates and two OR gates. Create a module\nin Verilog with the same functionality as the 7458 chip. It has 10 inputs\nand 2 outputs. You may choose to use an `assign` statement to drive each\nof the output wires, or you may choose to declare (four) wires for use as\nintermediate signals, where each internal wire is driven by the output of\none of the AND gates.\n\nIn this circuit, p1y should be the OR of two 3-input AND gates: one that\nANDs p1a, p1b, and p1c, and the second that ANDs p1d, p1e, and p1f. The\noutput p2y is the OR of two 2-input AND gates: one that ANDs p2a and p2b,\nand the second that ANDs p2c and p2d.\n\nmodule TopModule (\n input p1a,\n input p1b,\n input p1c,\n input p1d,\n input p1e,\n input p1f,\n output p1y,\n input p2a,\n input p2b,\n input p2c,\n input p2d,\n output p2y\n);\n\n", + "metadata": { + "file_size": 830, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob081_7458_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_239", + "file": "Prob126_circuit6_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [2:0] a,\n output reg [15:0] q\n);\n", + "metadata": { + "file_size": 62, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob126_circuit6_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_240", + "file": "Prob120_fsm3s_prompt.txt", + "task_type": "code_completion", + "content": "\nThe following is the state transition table for a Moore state machine\nwith one input, one output, and four states. Implement this state\nmachine. Include a synchronous active high reset that resets the FSM to\nstate A.\n\n State | Next state in=0, Next state in=1 | Output\n A | A, B | 0\n B | C, B | 0\n C | A, D | 0\n D | C, B | 1\n\nmodule TopModule (\n input clk,\n input in,\n input reset,\n output out\n);\n\n", + "metadata": { + "file_size": 536, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob120_fsm3s_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_241", + "file": "Prob143_fsm_onehot_prompt.txt", + "task_type": "code_completion", + "content": "\nGiven the follow state machine with 1 input and 2 outputs (the outputs\nare given as \"(out1, out2)\"):\n\n S0 (0, 0) --0--> S0\n S0 (0, 0) --1--> S1\n S1 (0, 0) --0--> S0\n S1 (0, 0) --1--> S2\n S2 (0, 0) --0--> S0\n S2 (0, 0) --1--> S3\n S3 (0, 0) --0--> S0\n S3 (0, 0) --1--> S4\n S4 (0, 0) --0--> S0\n S4 (0, 0) --1--> S5\n S5 (0, 0) --0--> S8\n S5 (0, 0) --1--> S6\n S6 (0, 0) --0--> S9\n S6 (0, 0) --1--> S7\n S7 (0, 1) --0--> S0\n S7 (0, 1) --1--> S7\n S8 (1, 0) --0--> S0\n S8 (1, 0) --1--> S1\n S9 (1, 1) --0--> S0\n S9 (1, 1) --1--> S1\n\nSuppose this state machine uses one-hot encoding, where state[0] through\nstate[9] correspond to the states S0 though S9, respectively. The outputs\nare zero unless otherwise specified.\n\nWrite Verilog implementing the state transition logic and output logic\nportions of the state machine (but not the state flip-flops). You are\ngiven the current state in state[9:0] and must produce next_state[9:0]\nand the two outputs. Derive the logic equations by inspection assuming a\none-hot encoding.\n\nmodule TopModule (\n input in,\n input [9:0] state,\n output [9:0] next_state,\n output out1,\n output out2\n);\n\n", + "metadata": { + "file_size": 1145, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob143_fsm_onehot_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_242", + "file": "Prob144_conwaylife_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input load,\n input [255:0] data,\n output reg [255:0] q\n);\n", + "metadata": { + "file_size": 95, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob144_conwaylife_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_243", + "file": "Prob026_alwaysblock1_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n output out_assign,\n output reg out_alwaysblock\n);\n", + "metadata": { + "file_size": 95, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob026_alwaysblock1_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_244", + "file": "Prob051_gates4_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a combinational circuit with four inputs, in[3:0]. There are 3\noutputs:\n\n (1) out_and: output of a 4-input AND gate.\n (2) out_or: output of a 4-input OR gate.\n (3) out_xor: output of a 4-input XOR gate.\n\nmodule TopModule (\n input [3:0] in,\n output out_and,\n output out_or,\n output out_xor\n);\n\n", + "metadata": { + "file_size": 307, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob051_gates4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_245", + "file": "Prob095_review2015_fsmshift_prompt.txt", + "task_type": "code_completion", + "content": "\nThis module is a part of the FSM for controlling the shift register, we\nwant the ability to enable the shift register for exactly 4 clock cycles\nwhenever the proper bit pattern is detected. Whenever the FSM is reset,\nassert shift_ena for 4 cycles, then 0 forever (until reset). Reset should\nbe active high synchronous.\n\nmodule TopModule (\n input clk,\n input reset,\n output shift_ena\n);\n\n", + "metadata": { + "file_size": 391, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob095_review2015_fsmshift_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_246", + "file": "Prob021_mux256to1v_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all\npacked into a single 1024-bit input vector. sel=0 should select bits\nin[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.\n\nmodule TopModule (\n input [1023:0] in,\n input [7:0] sel,\n output [3:0] out\n);\n\n", + "metadata": { + "file_size": 296, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob021_mux256to1v_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_247", + "file": "Prob093_ece241_2014_q3_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input c,\n input d,\n output [3:0] mux_in\n);\n", + "metadata": { + "file_size": 67, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob093_ece241_2014_q3_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_248", + "file": "Prob030_popcount255_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [254:0] in,\n output reg [7:0] out\n);\n", + "metadata": { + "file_size": 66, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob030_popcount255_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_249", + "file": "Prob029_m2014_q4g_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input in1,\n input in2,\n input in3,\n output logic out\n);\n", + "metadata": { + "file_size": 81, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob029_m2014_q4g_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_250", + "file": "Prob104_mt2015_muxdff_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input L,\n input q_in,\n input r_in,\n output reg Q\n);\n", + "metadata": { + "file_size": 90, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob104_mt2015_muxdff_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_251", + "file": "Prob118_history_shift_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input areset,\n input predict_valid,\n input predict_taken,\n output logic [31:0] predict_history,\n\n input train_mispredicted,\n input train_taken,\n input [31:0] train_history\n);\n", + "metadata": { + "file_size": 216, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob118_history_shift_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_252", + "file": "Prob002_m2014_q4i_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a circuit with no inputs and one output. That output should always\ndrive 0 (or logic low).\n\nmodule TopModule (\n output out\n);\n\n", + "metadata": { + "file_size": 135, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob002_m2014_q4i_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_253", + "file": "Prob006_vectorr_prompt.txt", + "task_type": "code_completion", + "content": "\nGiven an 8-bit input vector [7:0], reverse its bit ordering.\n\nmodule TopModule (\n input [7:0] in,\n output [7:0] out\n);\n\n", + "metadata": { + "file_size": 123, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob006_vectorr_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_254", + "file": "Prob074_ece241_2014_q4_prompt.txt", + "task_type": "code_completion", + "content": "\nGiven the finite state machine circuit described below, assume that the D\nflip-flops are initially reset to zero before the machine begins.\n\nBuild this circuit in Verilog.\n\nInput x goes to three different two-input gates: a XOR, an AND, and a OR\ngate. Each of the three gates is connected to the input of a D flip-flop\nand then the flip-flop outputs all go to a three-input NOR, whose output\nis Z. The second input of the XOR is its corresponding flip-flop's\noutput, the second input of the AND is its corresponding flip-flop's\ncomplemented output, and finally the second input of the OR is its\ncorresponding flip-flop's complementary output.\n\nmodule TopModule (\n input clk,\n input x,\n output z\n);\n\n", + "metadata": { + "file_size": 703, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob074_ece241_2014_q4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_255", + "file": "Prob127_lemmings1_prompt.txt", + "task_type": "code_completion", + "content": "\nThe game Lemmings involves critters with fairly simple brains. So simple\nthat we are going to model it using a finite state machine. In the\nLemmings' 2D world, Lemmings can be in one of two states: walking left\n(walk_left is 1) or walking right (walk_right is 1). It will switch\ndirections if it hits an obstacle. In particular, if a Lemming is bumped\non the left (by receiving a 1 on bump_left), it will walk right. If it's\nbumped on the right (by receiving a 1 on bump_right), it will walk left.\nIf it's bumped on both sides at the same time, it will still switch\ndirections. Implement a Moore state machine with two states, two inputs,\nand one output (internal to the module) that models this behaviour.\nareset is positive edge triggered asynchronous reseting the Lemming\nmachine to walk left.\n\nmodule TopModule (\n input clk,\n input areset,\n input bump_left,\n input bump_right,\n output walk_left,\n output walk_right\n);\n\n", + "metadata": { + "file_size": 930, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob127_lemmings1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_256", + "file": "Prob143_fsm_onehot_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input in,\n input [9:0] state,\n output [9:0] next_state,\n output out1,\n output out2\n);\n", + "metadata": { + "file_size": 112, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob143_fsm_onehot_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_257", + "file": "Prob124_rule110_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input load,\n input [511:0] data,\n output reg [511:0] q\n);\n", + "metadata": { + "file_size": 95, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob124_rule110_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_258", + "file": "Prob019_m2014_q4f_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input in1,\n input in2,\n output logic out\n);\n", + "metadata": { + "file_size": 68, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob019_m2014_q4f_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_259", + "file": "Prob007_wire_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input in,\n output out\n);\n", + "metadata": { + "file_size": 48, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob007_wire_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_260", + "file": "Prob085_shift4_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input areset,\n input load,\n input ena,\n input [3:0] data,\n output reg [3:0] q\n);\n", + "metadata": { + "file_size": 120, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob085_shift4_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_261", + "file": "Prob150_review2015_fsmonehot_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input d,\n input done_counting,\n input ack,\n input [9:0] state, // 10-bit one-hot current state\n output B3_next,\n output S_next,\n output S1_next,\n output Count_next,\n output Wait_next,\n output done,\n output counting,\n output shift_ena\n);\n", + "metadata": { + "file_size": 270, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob150_review2015_fsmonehot_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_262", + "file": "Prob010_mt2015_q4a_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement the boolean function z = (x^y) & x.\n\nmodule TopModule (\n input x,\n input y,\n output z\n);\n\n", + "metadata": { + "file_size": 104, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob010_mt2015_q4a_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_263", + "file": "Prob011_norgate_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n output out\n);\n", + "metadata": { + "file_size": 58, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob011_norgate_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_264", + "file": "Prob099_m2014_q6c_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [6:1] y,\n input w,\n output Y2,\n output Y4\n);\n", + "metadata": { + "file_size": 76, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob099_m2014_q6c_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_265", + "file": "Prob141_count_clock_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a set of counters suitable for use as a 12-hour clock (with am/pm\nindicator). Your counters are clocked by a fast-running clk, with a pulse\non ena whenever your clock should increment (i.e., once per second, while\n\"clk\" is much faster than once per second). The signal \"pm\" is asserted\nif the clock is PM, or is otherwise AM. hh, mm, and ss are two BCD\n(Binary- Coded Decimal) digits each for hours (01-12), minutes (00-59),\nand seconds (00-59). Reset is the active high synchronous signal that\nresets the clock to \"12:00 AM.\" Reset has higher priority than enable and\ncan occur even when not enabled.\n\nmodule TopModule (\n input clk,\n input reset,\n input ena,\n output reg pm,\n output reg [7:0] hh,\n output reg [7:0] mm,\n output reg [7:0] ss\n);\n\n", + "metadata": { + "file_size": 760, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob141_count_clock_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_266", + "file": "Prob128_fsm_ps2_prompt.txt", + "task_type": "code_completion", + "content": "\nThe PS/2 mouse protocol sends messages that are three bytes long.\nHowever, within a continuous byte stream, it's not obvious where messages\nstart and end. The only indication is that the first byte of each three\nbyte message always has in[3]=1 (but in[3] of the other two bytes may be\n1 or 0 depending on data). We want a finite state machine that will\nsearch for message boundaries when given an input byte stream. The\nalgorithm we'll use is to discard bytes until we see one with in[3]=1. We\nthen assume that this is byte 1 of a message, and signal the receipt of a\nmessage once all 3 bytes have been received (done). The FSM should signal\ndone in the cycle immediately after the third byte of each message was\nsuccessfully received. Reset should be active high synchronous.\n\nmodule TopModule (\n input clk,\n input [7:0] in,\n input reset,\n output done\n);\n\n", + "metadata": { + "file_size": 862, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob128_fsm_ps2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_267", + "file": "Prob115_shift18_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input load,\n input ena,\n input [1:0] amount,\n input [63:0] data,\n output reg [63:0] q\n);\n", + "metadata": { + "file_size": 128, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob115_shift18_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_268", + "file": "Prob098_circuit7_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input a,\n output reg q\n);\n", + "metadata": { + "file_size": 62, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob098_circuit7_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_269", + "file": "Prob047_dff8ar_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input [7:0] d,\n input areset,\n output reg [7:0] q\n);\n", + "metadata": { + "file_size": 90, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob047_dff8ar_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_270", + "file": "Prob088_ece241_2014_q5b_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input areset,\n input x,\n output z\n);\n", + "metadata": { + "file_size": 74, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob088_ece241_2014_q5b_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_271", + "file": "Prob112_always_case2_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [3:0] in,\n output reg [1:0] pos\n);\n", + "metadata": { + "file_size": 64, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob112_always_case2_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_272", + "file": "Prob112_always_case2_prompt.txt", + "task_type": "code_completion", + "content": "\nA priority encoder is a combinational circuit that, when given an input\nbit vector, outputs the position of the first 1 bit in the vector. For\nexample, a 8-bit priority encoder given the input 8'b10010000 would\noutput 3'd4, because bit[4] is first bit that is high. Build a 4-bit\npriority encoder. For this problem, if none of the input bits are high\n(i.e., input is zero), output zero. Note that a 4-bit number has 16\npossible combinations.\n\nmodule TopModule (\n input [3:0] in,\n output reg [1:0] pos\n);\n\n", + "metadata": { + "file_size": 508, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob112_always_case2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_273", + "file": "Prob043_vector5_prompt.txt", + "task_type": "code_completion", + "content": "\nGiven five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise\none- bit comparisons in the 25-bit output vector. The output should be 1\nif the two bits being compared are equal. Example: out[24] = ~a ^ a;\nout[23] = ~a ^ b; out[22] = ~a ^ c; ... out[ 1] = ~e ^ d; out[ 0] = ~e ^\ne.\n\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n input e,\n output [24:0] out\n);\n\n", + "metadata": { + "file_size": 388, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob043_vector5_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_274", + "file": "Prob058_alwaysblock2_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild an XOR gate three ways, using an assign statement (output\nout_assign), a combinational always block (output out_always_comb), and a\nclocked always block (output out_always_ff). Note that the clocked always\nblock produces a different circuit from the other two: There is a flip-\nflop so the output is delayed.\n\nmodule TopModule (\n input clk,\n input a,\n input b,\n output out_assign,\n output reg out_always_comb,\n output reg out_always_ff\n);\n\n", + "metadata": { + "file_size": 453, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob058_alwaysblock2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_275", + "file": "Prob045_edgedetect2_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input [7:0] in,\n output reg [7:0] anyedge\n);\n", + "metadata": { + "file_size": 81, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob045_edgedetect2_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_276", + "file": "Prob092_gatesv100_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [99:0] in,\n output [98:0] out_both,\n output [99:1] out_any,\n output [99:0] out_different\n);\n", + "metadata": { + "file_size": 123, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob092_gatesv100_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_277", + "file": "Prob038_count15_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n output reg [3:0] q\n);\n", + "metadata": { + "file_size": 72, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob038_count15_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_278", + "file": "Prob063_review2015_shiftcount_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input shift_ena,\n input count_ena,\n input data,\n output reg [3:0] q\n);\n", + "metadata": { + "file_size": 109, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob063_review2015_shiftcount_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_279", + "file": "Prob128_fsm_ps2_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input [7:0] in,\n input reset,\n output done\n);\n", + "metadata": { + "file_size": 83, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob128_fsm_ps2_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_280", + "file": "Prob010_mt2015_q4a_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input x,\n input y,\n output z\n);\n", + "metadata": { + "file_size": 56, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob010_mt2015_q4a_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_281", + "file": "Prob028_m2014_q4a_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement a D latch using an always block.\n\nmodule TopModule (\n input d,\n input ena,\n output logic q\n);\n\n", + "metadata": { + "file_size": 109, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob028_m2014_q4a_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_282", + "file": "Prob045_edgedetect2_prompt.txt", + "task_type": "code_completion", + "content": "\nFor each bit in an 8-bit vector, detect when the input signal changes\nfrom one clock cycle to the next (detect any edge). The output bit should\nbe set the cycle after a 0 to 1 or 1 to 0 transition occurs.\n\nmodule TopModule (\n input clk,\n input [7:0] in,\n output reg [7:0] anyedge\n);\n\n", + "metadata": { + "file_size": 288, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob045_edgedetect2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_283", + "file": "Prob108_rule90_prompt.txt", + "task_type": "code_completion", + "content": "\nRule 90 is a one-dimensional cellular automaton with interesting\nproperties. The rules are simple. There is a one-dimensional array of\ncells (on or off). At each time step, the next state of each cell is the\nXOR of the cell's two current neighbours:\n\n Left | Center | Right | Center's next state\n 1 | 1 | 1 | 0\n 1 | 1 | 0 | 1\n 1 | 0 | 1 | 0\n 1 | 0 | 0 | 1\n 0 | 1 | 1 | 1\n 0 | 1 | 0 | 0\n 0 | 0 | 1 | 1\n 0 | 0 | 0 | 0\n\nIn this circuit, create a 512-cell system (q[511:0]), and advance by one\ntime step each clock cycle. The load input indicates the state of the\nsystem should be loaded with data[511:0]. Assume the boundaries (q[-1]\nand q[512]) are both zero (off).\n\nmodule TopModule (\n input clk,\n input load,\n input [511:0] data,\n output reg [511:0] q\n);\n\n", + "metadata": { + "file_size": 866, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob108_rule90_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_284", + "file": "Prob080_timer_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input load,\n input [9:0] data,\n output tc\n);\n", + "metadata": { + "file_size": 82, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob080_timer_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_285", + "file": "Prob030_popcount255_prompt.txt", + "task_type": "code_completion", + "content": "\nA \"population count\" circuit counts the number of '1's in an input\nvector. Build a population count circuit for a 255-bit input vector.\n\nmodule TopModule (\n input [254:0] in,\n output reg [7:0] out\n);\n\n", + "metadata": { + "file_size": 204, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob030_popcount255_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_286", + "file": "Prob086_lfsr5_prompt.txt", + "task_type": "code_completion", + "content": "\nA linear feedback shift register is a shift register usually with a few\nXOR gates to produce the next state of the shift register. A Galois LFSR\nis one particular arrangement that shifts right, where a bit position with\na \"tap\" is XORed with the LSB output bit (q[0]) to produce its next value,\nwhile bit positions without a tap shift right unchanged. If the taps positions\nare carefully chosen, the LFSR can be made to be \"maximum-length\". A maximum-length\nLFSR of n bits cycles through 2**n-1 states before repeating (the all-zero state is\nnever reached). Build a 5-bit maximal-length Galois LFSR with taps at bit\npositions 5 and 3. The active-high synchronous reset should reset the\nLFSR output to 1.\n\nmodule TopModule (\n input clk,\n input reset,\n output reg [4:0] q\n);\n\n", + "metadata": { + "file_size": 778, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob086_lfsr5_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_287", + "file": "Prob156_review2015_fancytimer_prompt.txt", + "task_type": "code_completion", + "content": "\nWe want to create a timer with one input that:\n\n (1) is started when a particular input pattern (1101) is detected,\n (2) shifts in 4 more bits to determine the duration to delay,\n (3) waits for the counters to finish counting, and\n (4) notifies the user and waits for the user to acknowledge the timer.\n\nThe serial data is available on the data input pin. When the pattern 1101\nis received, the circuit must then shift in the next 4 bits,\nmost-significant-bit first. These 4 bits determine the duration of the\ntimer delay, referred to as delay[3:0]. After that, the state machine\nasserts its counting output to indicate it is counting. Once the 1101 and\ndelay[3:0] have been read, the circuit no longer looks at the data input\nuntil it resumes searching after everything else is done.\n\nThe state machine must count for exactly (delay[3:0] + 1) * 1000 clock\ncycles. e.g., delay=0 means count 1000 cycles, and delay=5 means count\n6000 cycles. Also output the current remaining time. This should be equal\nto delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until\nit is 0 for 1000 cycles.\n\nWhen the circuit isn't counting, the count[3:0] output is don't-care\n(whatever value is convenient for you to implement). At that point, the\ncircuit must assert done to notify the user the timer has timed out, and\nwaits until input ack is 1 before being reset to look for the next\noccurrence of the start sequence (1101).\n\nThe circuit should reset into a state where it begins searching for the\ninput sequence 1101. The reset signal is active high synchronous.\n\nmodule TopModule (\n input wire clk,\n input wire reset,\n input wire data,\n output wire [3:0] count,\n output reg counting,\n output reg done,\n input wire ack\n);\n\n", + "metadata": { + "file_size": 1733, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob156_review2015_fancytimer_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_288", + "file": "Prob055_conditional_prompt.txt", + "task_type": "code_completion", + "content": "\nGiven four unsigned numbers, find the minimum. Unsigned numbers can be\ncompared with standard comparison operators (a < b).\n\nmodule TopModule (\n input [7:0] a,\n input [7:0] b,\n input [7:0] c,\n input [7:0] d,\n output reg [7:0] min\n);\n\n", + "metadata": { + "file_size": 240, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob055_conditional_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_289", + "file": "Prob096_review2015_fsmseq_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n input data,\n output start_shifting\n);\n", + "metadata": { + "file_size": 89, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob096_review2015_fsmseq_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_290", + "file": "Prob079_fsm3onehot_prompt.txt", + "task_type": "code_completion", + "content": "\nThe following is the state transition table for a Moore state machine\nwith one input, one output, and four states. Use the following one-hot\nstate encoding: A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000. Derive state\ntransition and output logic equations by inspection assuming a one-hot\nencoding. Implement only the state transition logic and output logic (the\ncombinational logic portion) for this state machine.\n\n State | Next state in=0, Next state in=1 | Output\n A | A, B | 0\n B | C, B | 0\n C | A, D | 0\n D | C, B | 1\n\nmodule TopModule (\n input in,\n input [3:0] state,\n output reg [3:0] next_state,\n output out\n);\n\n", + "metadata": { + "file_size": 755, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob079_fsm3onehot_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_291", + "file": "Prob067_countslow_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input slowena,\n input reset,\n output reg [3:0] q\n);\n", + "metadata": { + "file_size": 89, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob067_countslow_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_292", + "file": "Prob016_m2014_q4j_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement a 4-bit adder with full adders. The output sum should include\nthe overflow bit.\n\nmodule TopModule (\n input [3:0] x,\n input [3:0] y,\n output [4:0] sum\n);\n\n", + "metadata": { + "file_size": 168, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob016_m2014_q4j_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_293", + "file": "Prob040_count10_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n output reg [3:0] q\n);\n", + "metadata": { + "file_size": 72, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob040_count10_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_294", + "file": "Prob073_dff16e_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate 16 D flip-flops. It's sometimes useful to only modify parts of a\ngroup of flip-flops. The byte-enable inputs control whether each byte of\nthe 16 registers should be written to on that cycle. byteena[1] controls\nthe upper byte d[15:8], while byteena[0] controls the lower byte d[7:0].\nresetn is a synchronous, active-low reset. All DFFs should be triggered\nby the positive edge of clk.\n\nmodule TopModule (\n input clk,\n input resetn,\n input [1:0] byteena,\n input [15:0] d,\n output reg [15:0] q\n);\n\n", + "metadata": { + "file_size": 509, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob073_dff16e_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_295", + "file": "Prob083_mt2015_q4b_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input x,\n input y,\n output z\n);\n", + "metadata": { + "file_size": 56, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob083_mt2015_q4b_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_296", + "file": "Prob001_zero_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n output zero\n);\n", + "metadata": { + "file_size": 37, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob001_zero_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_297", + "file": "Prob111_fsm2s_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input j,\n input k,\n input reset,\n output out\n);\n", + "metadata": { + "file_size": 86, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob111_fsm2s_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_298", + "file": "Prob134_2014_q3c_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input x,\n input [2:0] y,\n output reg Y0,\n output reg z\n);\n", + "metadata": { + "file_size": 96, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob134_2014_q3c_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_299", + "file": "Prob145_circuit8_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clock,\n input a,\n output reg p,\n output reg q\n);\n", + "metadata": { + "file_size": 80, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob145_circuit8_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_300", + "file": "Prob100_fsm3comb_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input in,\n input [1:0] state,\n output reg [1:0] next_state,\n output out\n);\n", + "metadata": { + "file_size": 100, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob100_fsm3comb_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_301", + "file": "Prob048_m2014_q4c_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement a simple D flip flop with active high synchronous reset (reset\noutput to 0).\n\nmodule TopModule (\n input clk,\n input d,\n input r,\n output logic q\n);\n\n", + "metadata": { + "file_size": 164, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob048_m2014_q4c_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_302", + "file": "Prob014_andgate_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a module that implements an AND gate.\n\nmodule TopModule (\n input a,\n input b,\n output out\n);\n\n", + "metadata": { + "file_size": 105, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob014_andgate_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_303", + "file": "Prob116_m2014_q3_prompt.txt", + "task_type": "code_completion", + "content": "\nConsider the function f shown in the Karnaugh map below. d is don't-care,\nwhich means you may choose to output whatever value is convenient.\nImplement this function.\n\n x[1]x[2]\n x[3]x[4] 00 01 11 10\n 00 | d | 0 | d | d |\n 01 | 0 | d | 1 | 0 |\n 11 | 1 | 1 | d | d |\n 10 | 1 | 1 | 0 | d |\n\nmodule TopModule (\n input [4:1] x,\n output logic f\n);\n\n", + "metadata": { + "file_size": 395, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob116_m2014_q3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_304", + "file": "Prob005_notgate_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a module that implements a NOT gate.\n\nmodule TopModule (\n input in,\n output out\n);\n\n", + "metadata": { + "file_size": 94, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob005_notgate_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_305", + "file": "Prob022_mux2to1_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input sel,\n output out\n);\n", + "metadata": { + "file_size": 71, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob022_mux2to1_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_306", + "file": "Prob075_counter_2bc_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input areset,\n input train_valid,\n input train_taken,\n output logic [1:0] state\n);\n", + "metadata": { + "file_size": 121, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob075_counter_2bc_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_307", + "file": "Prob144_conwaylife_prompt.txt", + "task_type": "code_completion", + "content": "\nThe \"game\" is played on a two-dimensional grid of cells, where each cell\nis either 1 (alive) or 0 (dead). At each time step, each cell changes\nstate depending on how many neighbours it has:\n\n (1) 0-1 neighbour: Cell becomes 0.\n (2) 2 neighbours: Cell state does not change.\n (3) 3 neighbours: Cell becomes 1.\n (4) 4+ neighbours: Cell becomes 0.\n\nThe game is formulated for an infinite grid. In this circuit, we will use\na 16x16 grid. To make things more interesting, we will use a 16x16\ntoroid, where the sides wrap around to the other side of the grid. For\nexample, the corner cell (0,0) has 8 neighbours: (15,1), (15,0), (15,15),\n(0,1), (0,15), (1,1), (1,0), and (1,15). The 16x16 grid is represented by\na length 256 vector, where each row of 16 cells is represented by a\nsub-vector: q[15:0] is row 0, q[31:16] is row 1, etc.\n\n (1) load: Loads data into q at the next clock edge, for loading initial\n state. Active high synchronous.\n (2) q: The 16x16 current state of the game, updated every clock cycle.\n\nThe game state should advance by one timestep every clock cycle.\n\nmodule TopModule (\n input clk,\n input load,\n input [255:0] data,\n output reg [255:0] q\n);\n\n", + "metadata": { + "file_size": 1182, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob144_conwaylife_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_308", + "file": "Prob147_circuit10_prompt.txt", + "task_type": "code_completion", + "content": "\nThis is a sequential circuit. The circuit consists of combinational logic\nand one bit of memory (i.e., one flip-flop). The output of the flip-flop\nhas been made observable through the output state.\n\n Read the simulation waveforms to determine what the circuit does, then implement it.\n\n time clk a b state q\n 0ns 0 1 x x x\n 5ns 1 1 x x x\n 10ns 0 0 0 x x\n 15ns 1 0 0 0 0\n 20ns 0 0 0 0 0\n 25ns 1 0 0 0 0\n 30ns 0 0 0 0 0\n 35ns 1 0 0 0 0\n 40ns 0 0 0 0 0\n 45ns 1 0 1 0 1\n 50ns 0 0 1 0 1\n 55ns 1 1 0 0 1\n 60ns 0 1 0 0 1\n 65ns 1 1 1 0 0\n 70ns 0 1 1 0 0\n 75ns 1 0 0 1 1\n 80ns 0 0 0 1 1\n 85ns 1 1 1 0 0\n 90ns 0 1 1 0 0\n 95ns 1 1 1 1 1\n 100ns 0 1 1 1 1\n 105ns 1 1 1 1 1\n 110ns 0 1 1 1 1\n 115ns 1 1 0 1 0\n 120ns 0 1 0 1 0\n 125ns 1 0 1 1 0\n 130ns 0 0 1 1 0\n 135ns 1 0 0 1 1\n 140ns 0 0 0 1 1\n 145ns 1 0 0 0 0\n 150ns 0 0 0 0 0\n 155ns 1 0 0 0 0\n 160ns 0 0 0 0 0\n 165ns 1 0 0 0 0\n 170ns 0 0 0 0 0\n 175ns 1 0 0 0 0\n 180ns 0 0 0 0 0\n 185ns 1 0 0 0 0\n 190ns 0 0 0 0 0\n\nmodule TopModule (\n input clk,\n input a,\n input b,\n output q,\n output state\n);\n\n", + "metadata": { + "file_size": 3734, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob147_circuit10_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_309", + "file": "Prob052_gates100_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [99:0] in,\n output out_and,\n output out_or,\n output out_xor\n);\n", + "metadata": { + "file_size": 94, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob052_gates100_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_310", + "file": "Prob119_fsm3_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input in,\n input areset,\n output out\n);\n", + "metadata": { + "file_size": 77, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob119_fsm3_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_311", + "file": "Prob050_kmap1_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input c,\n output out\n);\n", + "metadata": { + "file_size": 69, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob050_kmap1_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_312", + "file": "Prob148_2013_q2afsm_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input resetn,\n input [3:1] r,\n output [3:1] g\n);\n", + "metadata": { + "file_size": 86, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob148_2013_q2afsm_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_313", + "file": "Prob114_bugs_case_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [7:0] code,\n output reg [3:0] out,\n output reg valid\n);\n", + "metadata": { + "file_size": 86, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob114_bugs_case_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_314", + "file": "Prob078_dualedge_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input d,\n output reg q\n);\n", + "metadata": { + "file_size": 62, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob078_dualedge_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_315", + "file": "Prob015_vector1_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [15:0] in,\n output [7:0] out_hi,\n output [7:0] out_lo\n);\n", + "metadata": { + "file_size": 87, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob015_vector1_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_316", + "file": "Prob091_2012_q2b_prompt.txt", + "task_type": "code_completion", + "content": "\nConsider the state machine shown below:\n\n A (0) --1--> B\n A (0) --0--> A\n B (0) --1--> C\n B (0) --0--> D\n C (0) --1--> E\n C (0) --0--> D\n D (0) --1--> F\n D (0) --0--> A\n E (1) --1--> E\n E (1) --0--> D\n F (1) --1--> C\n F (1) --0--> D\n\nAssume that a one-hot code is used with the state assignment y[5:0] =\n000001(A), 000010(B), 000100(C), 001000(D), 010000(E), 100000(F)\n\nWrite a Verilog for the signal Y1, which is the input of state flip-flop\ny[1], for the signal Y3, which is the input of state flip-flop y[3].\nDerive the Verilog by inspection assuming a one-hot encoding.\n\nmodule TopModule (\n input [5:0] y,\n input w,\n output Y1,\n output Y3\n);\n\n", + "metadata": { + "file_size": 664, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob091_2012_q2b_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_317", + "file": "Prob025_reduction_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [7:0] in,\n output parity\n);\n", + "metadata": { + "file_size": 57, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob025_reduction_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_318", + "file": "Prob071_always_casez_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [7:0] in,\n output reg [2:0] pos\n);\n", + "metadata": { + "file_size": 64, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob071_always_casez_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_319", + "file": "Prob024_hadd_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a half adder. A half adder adds two bits (with no carry-in) and\nproduces a sum and carry-out.\n\nmodule TopModule (\n input a,\n input b,\n output sum,\n output cout\n);\n\n", + "metadata": { + "file_size": 176, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob024_hadd_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_320", + "file": "Prob046_dff8p_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate 8 D flip-flops with active high synchronous reset. The flip-flops\nmust be reset to 0x34 rather than zero. All DFFs should be triggered by\nthe negative edge of clk.\n\nmodule TopModule (\n input clk,\n input [7:0] d,\n input reset,\n output reg [7:0] q\n);\n\n", + "metadata": { + "file_size": 262, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob046_dff8p_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_321", + "file": "Prob031_dff_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a single D flip-flop.\n\nmodule TopModule (\n input clk,\n input d,\n output reg q\n);\n\n", + "metadata": { + "file_size": 93, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob031_dff_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_322", + "file": "Prob009_popcount3_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [2:0] in,\n output [1:0] out\n);\n", + "metadata": { + "file_size": 60, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob009_popcount3_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_323", + "file": "Prob044_vectorgates_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a circuit that has two 3-bit inputs that computes the bitwise-OR of\nthe two vectors, the logical-OR of the two vectors, and the inverse (NOT)\nof both vectors. Place the inverse of b in the upper half of out_not\n(i.e., bits [5:3]), and the inverse of a in the lower half.\n\nmodule TopModule (\n input [2:0] a,\n input [2:0] b,\n output [2:0] out_or_bitwise,\n output out_or_logical,\n output [5:0] out_not\n);\n\n", + "metadata": { + "file_size": 415, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob044_vectorgates_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_324", + "file": "Prob088_ece241_2014_q5b_prompt.txt", + "task_type": "code_completion", + "content": "\nThe following diagram is a Mealy machine implementation of the 2's\ncomplementer. Implement in Verilog using one-hot encoding. Resets into\nstate A and reset is asynchronous active-high.\n\n A --x=0 (z=0)--> A\n A --x=1 (z=1)--> B\n B --x=0 (z=1)--> B\n B --x=1 (z=0)--> B\n\nmodule TopModule (\n input clk,\n input areset,\n input x,\n output z\n);\n\n", + "metadata": { + "file_size": 346, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob088_ece241_2014_q5b_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_325", + "file": "Prob017_mux2to1v_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a 2-1 multiplexer. When sel=0, choose a. When sel=1, choose b.\n\nmodule TopModule (\n input [99:0] a,\n input [99:0] b,\n input sel,\n output [99:0] out\n);\n\n", + "metadata": { + "file_size": 164, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob017_mux2to1v_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_326", + "file": "Prob041_dff8r_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input [7:0] d,\n input reset,\n output reg [7:0] q\n);\n", + "metadata": { + "file_size": 89, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob041_dff8r_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_327", + "file": "Prob136_m2014_q6_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n input w,\n output z\n);\n", + "metadata": { + "file_size": 73, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob136_m2014_q6_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_328", + "file": "Prob074_ece241_2014_q4_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input x,\n output z\n);\n", + "metadata": { + "file_size": 58, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob074_ece241_2014_q4_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_329", + "file": "Prob072_thermostat_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input mode,\n input too_cold,\n input too_hot,\n input fan_on,\n output heater,\n output aircon,\n output fan\n);\n", + "metadata": { + "file_size": 135, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob072_thermostat_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_330", + "file": "Prob125_kmap3_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output reg out\n);\n", + "metadata": { + "file_size": 84, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob125_kmap3_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_331", + "file": "Prob036_ringer_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input ring,\n input vibrate_mode,\n output ringer,\n output motor\n);\n", + "metadata": { + "file_size": 91, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob036_ringer_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_332", + "file": "Prob050_kmap1_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement the circuit described by the Karnaugh map below.\n\n a\n bc 0 1\n 00 | 0 | 1 |\n 01 | 1 | 1 |\n 11 | 1 | 1 |\n 10 | 1 | 1 |\n\nmodule TopModule (\n input a,\n input b,\n input c,\n output out\n);\n\n", + "metadata": { + "file_size": 221, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob050_kmap1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_333", + "file": "Prob097_mux9to1v_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses\nb, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.\n\nmodule TopModule (\n input [15:0] a,\n input [15:0] b,\n input [15:0] c,\n input [15:0] d,\n input [15:0] e,\n input [15:0] f,\n input [15:0] g,\n input [15:0] h,\n input [15:0] i,\n input [3:0] sel,\n output logic [15:0] out\n);\n\n", + "metadata": { + "file_size": 377, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob097_mux9to1v_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_334", + "file": "Prob003_step_one_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n output one\n);\n", + "metadata": { + "file_size": 36, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob003_step_one_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_335", + "file": "Prob130_circuit5_prompt.txt", + "task_type": "code_completion", + "content": "\nThis is a combinational circuit. Read the simulation waveforms to\ndetermine what the circuit does, then implement it.\n\n time a b c d e q\n 0ns x x x x x x\n 5ns x x x x x x\n 10ns x x x x x x\n 15ns a b 0 d e b\n 20ns a b 1 d e e\n 25ns a b 2 d e a\n 30ns a b 3 d e d\n 35ns a b 4 d e f\n 40ns a b 5 d e f\n 45ns a b 6 d e f\n 50ns a b 7 d e f\n 55ns a b 8 d e f\n 60ns a b 9 d e f\n 65ns a b a d e f\n 70ns a b b d e f\n 75ns a b c d e f\n 80ns a b d d e f\n 85ns a b e d e f\n 90ns a b f d e f\n\nmodule TopModule (\n input [3:0] a,\n input [3:0] b,\n input [3:0] c,\n input [3:0] d,\n input [3:0] e,\n output reg [3:0] q\n);\n\n", + "metadata": { + "file_size": 750, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob130_circuit5_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_336", + "file": "Prob057_kmap2_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement the circuit described by the Karnaugh map below.\n\n ab\n cd 00 01 11 10\n 00 | 1 | 1 | 0 | 1 |\n 01 | 1 | 0 | 0 | 1 |\n 11 | 0 | 1 | 1 | 1 |\n 10 | 1 | 1 | 0 | 0 |\n\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output out\n);\n\n", + "metadata": { + "file_size": 278, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob057_kmap2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_337", + "file": "Prob039_always_if_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input sel_b1,\n input sel_b2,\n output out_assign,\n output reg out_always\n);\n", + "metadata": { + "file_size": 122, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob039_always_if_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_338", + "file": "Prob018_mux256to1_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [255:0] in,\n input [7:0] sel,\n output out\n);\n", + "metadata": { + "file_size": 76, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob018_mux256to1_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_339", + "file": "Prob013_m2014_q4e_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input in1,\n input in2,\n output logic out\n);\n", + "metadata": { + "file_size": 68, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob013_m2014_q4e_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_340", + "file": "Prob070_ece241_2013_q2_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output out_sop,\n output out_pos\n);\n", + "metadata": { + "file_size": 102, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob070_ece241_2013_q2_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_341", + "file": "Prob023_vector100r_prompt.txt", + "task_type": "code_completion", + "content": "\nGiven a 100-bit input vector [99:0], reverse its bit ordering.\n\na\n\nmodule TopModule (\n input [99:0] in,\n output reg [99:0] out\n);\n\n", + "metadata": { + "file_size": 134, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob023_vector100r_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_342", + "file": "problems.txt", + "task_type": "code_completion", + "content": "Prob001_zero\nProb002_m2014_q4i\nProb003_step_one\nProb004_vector2\nProb005_notgate\nProb006_vectorr\nProb007_wire\nProb008_m2014_q4h\nProb009_popcount3\nProb010_mt2015_q4a\nProb011_norgate\nProb012_xnorgate\nProb013_m2014_q4e\nProb014_andgate\nProb015_vector1\nProb016_m2014_q4j\nProb017_mux2to1v\nProb018_mux256to1\nProb019_m2014_q4f\nProb020_mt2015_eq2\nProb021_mux256to1v\nProb022_mux2to1\nProb023_vector100r\nProb024_hadd\nProb025_reduction\nProb026_alwaysblock1\nProb027_fadd\nProb028_m2014_q4a\nProb029_m2014_q4g\nProb030_popcount255\nProb031_dff\nProb032_vector0\nProb033_ece241_2014_q1c\nProb034_dff8\nProb035_count1to10\nProb036_ringer\nProb037_review2015_count1k\nProb038_count15\nProb039_always_if\nProb040_count10\nProb041_dff8r\nProb042_vector4\nProb043_vector5\nProb044_vectorgates\nProb045_edgedetect2\nProb046_dff8p\nProb047_dff8ar\nProb048_m2014_q4c\nProb049_m2014_q4b\nProb050_kmap1\nProb051_gates4\nProb052_gates100\nProb053_m2014_q4d\nProb054_edgedetect\nProb055_conditional\nProb056_ece241_2013_q7\nProb057_kmap2\nProb058_alwaysblock2\nProb059_wire4\nProb060_m2014_q4k\nProb061_2014_q4a\nProb062_bugs_mux2\nProb063_review2015_shiftcount\nProb064_vector3\nProb065_7420\nProb066_edgecapture\nProb067_countslow\nProb068_countbcd\nProb069_truthtable1\nProb070_ece241_2013_q2\nProb071_always_casez\nProb072_thermostat\nProb073_dff16e\nProb074_ece241_2014_q4\nProb075_counter_2bc\nProb076_always_case\nProb077_wire_decl\nProb078_dualedge\nProb079_fsm3onehot\nProb080_timer\nProb081_7458\nProb082_lfsr32\nProb083_mt2015_q4b\nProb084_ece241_2013_q12\nProb085_shift4\nProb086_lfsr5\nProb087_gates\nProb088_ece241_2014_q5b\nProb089_ece241_2014_q5a\nProb090_circuit1\nProb091_2012_q2b\nProb092_gatesv100\nProb093_ece241_2014_q3\nProb094_gatesv\nProb095_review2015_fsmshift\nProb096_review2015_fsmseq\nProb097_mux9to1v\nProb098_circuit7\nProb099_m2014_q6c\nProb100_fsm3comb\nProb101_circuit4\nProb102_circuit3\nProb103_circuit2\nProb104_mt2015_muxdff\nProb105_rotate100\nProb106_always_nolatches\nProb107_fsm1s\nProb108_rule90\nProb109_fsm1\nProb110_fsm2\nProb111_fsm2s\nProb112_always_case2\nProb113_2012_q1g\nProb114_bugs_case\nProb115_shift18\nProb116_m2014_q3\nProb117_circuit9\nProb118_history_shift\nProb119_fsm3\nProb120_fsm3s\nProb121_2014_q3bfsm\nProb122_kmap4\nProb123_bugs_addsubz\nProb124_rule110\nProb125_kmap3\nProb126_circuit6\nProb127_lemmings1\nProb128_fsm_ps2\nProb129_ece241_2013_q8\nProb130_circuit5\nProb131_mt2015_q4\nProb132_always_if2\nProb133_2014_q3fsm\nProb134_2014_q3c\nProb135_m2014_q6b\nProb136_m2014_q6\nProb137_fsm_serial\nProb138_2012_q2fsm\nProb139_2013_q2bfsm\nProb140_fsm_hdlc\nProb141_count_clock\nProb142_lemmings2\nProb143_fsm_onehot\nProb144_conwaylife\nProb145_circuit8\nProb146_fsm_serialdata\nProb147_circuit10\nProb148_2013_q2afsm\nProb149_ece241_2013_q4\nProb150_review2015_fsmonehot\nProb151_review2015_fsm\nProb152_lemmings3\nProb153_gshare\nProb154_fsm_ps2data\nProb155_lemmings4\nProb156_review2015_fancytimer\n", + "metadata": { + "file_size": 2814, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/problems.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_343", + "file": "Prob079_fsm3onehot_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input in,\n input [3:0] state,\n output reg [3:0] next_state,\n output out\n);\n", + "metadata": { + "file_size": 100, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob079_fsm3onehot_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_344", + "file": "Prob101_circuit4_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output q\n);\n", + "metadata": { + "file_size": 78, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob101_circuit4_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_345", + "file": "Prob100_fsm3comb_prompt.txt", + "task_type": "code_completion", + "content": "\nThe following is the state transition table for a Moore state machine\nwith one input, one output, and four states. Use the following state\nencoding: A=2'b00, B=2'b01, C=2'b10, D=2'b11.Implement only the state\ntransition logic and output logic (the combinational logic portion) for\nthis state machine. Given the current state (state), compute the\nnext_state and output (out) based on the state transition table.\n\n State | Next state in=0, Next state in=1 | Output\n A | A, B | 0\n B | C, B | 0\n C | A, D | 0\n D | C, B | 1\n\nmodule TopModule (\n input in,\n input [1:0] state,\n output reg [1:0] next_state,\n output out\n);\n\n", + "metadata": { + "file_size": 754, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob100_fsm3comb_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_346", + "file": "Prob122_kmap4_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement the circuit described by the Karnaugh map below.\n\n ab\n cd 00 01 11 10\n 00 | 0 | 1 | 0 | 1 |\n 01 | 1 | 0 | 1 | 0 |\n 11 | 0 | 1 | 0 | 1 |\n 10 | 1 | 0 | 1 | 0 |\n\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output reg out\n);\n\n", + "metadata": { + "file_size": 276, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob122_kmap4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_347", + "file": "Prob121_2014_q3bfsm_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n input x,\n output reg z\n);\n", + "metadata": { + "file_size": 77, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob121_2014_q3bfsm_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_348", + "file": "Prob015_vector1_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a combinational circuit that splits an input half-word (16 bits,\n[15:0] ) into lower [7:0] and upper [15:8] bytes.\n\nmodule TopModule (\n input [15:0] in,\n output [7:0] out_hi,\n output [7:0] out_lo\n);\n\n", + "metadata": { + "file_size": 210, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob015_vector1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_349", + "file": "Prob130_circuit5_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [3:0] a,\n input [3:0] b,\n input [3:0] c,\n input [3:0] d,\n input [3:0] e,\n output reg [3:0] q\n);\n", + "metadata": { + "file_size": 129, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob130_circuit5_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_350", + "file": "Prob062_bugs_mux2_prompt.txt", + "task_type": "code_completion", + "content": "\nFind the bug and fix this 8-bit wide 2-to-1 mux.\n\n module top_module (\n input sel,\n input [7:0] a,\n input [7:0] b,\n output out );\n\n assign out = (~sel & a) | (sel & b);\n\n endmodule\n\nmodule TopModule (\n input sel,\n input [7:0] a,\n input [7:0] b,\n output reg [7:0] out\n);\n\n", + "metadata": { + "file_size": 304, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob062_bugs_mux2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_351", + "file": "Prob082_lfsr32_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n output reg [31:0] q\n);\n", + "metadata": { + "file_size": 73, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob082_lfsr32_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_352", + "file": "Prob043_vector5_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n input e,\n output [24:0] out\n);\n", + "metadata": { + "file_size": 98, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob043_vector5_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_353", + "file": "Prob114_bugs_case_prompt.txt", + "task_type": "code_completion", + "content": "\nThis combinational circuit is supposed to recognize 8-bit keyboard\nscancodes for keys 0 through 9. It should indicate whether one of the 10\ncases were recognized (valid), and if so, which key was detected. If the\n8-bit input is 8'h45, 8'h16, 8'h1e, 8'h26, 8'h25, 8'h2e, 8'h36, 8'h3d,\n8'h3e, or 8'h46, the 4-bit output will be set to 0, 1, 2, 3, 4, 5, 6, 7,\n8, or 9 respectively, the 1-bit valid would be set to 1. If the input\ndoes not match any of the cases, both output signals would be set to 0.\n\nmodule TopModule (\n input [7:0] code,\n output reg [3:0] out,\n output reg valid\n);\n\n", + "metadata": { + "file_size": 587, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob114_bugs_case_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_354", + "file": "Prob090_circuit1_prompt.txt", + "task_type": "code_completion", + "content": "\nThis is a combinational circuit. Read the simulation waveforms to\ndetermine what the circuit does, then implement it.\n\n time a b q\n 0ns 0 0 0\n 5ns 0 0 0\n 10ns 0 0 0\n 15ns 0 0 0\n 20ns 0 0 0\n 25ns 0 1 0\n 30ns 0 1 0\n 35ns 1 0 0\n 40ns 1 0 0\n 45ns 1 1 1\n 50ns 1 1 1\n 55ns 0 0 0\n 60ns 0 0 0\n 65ns 0 1 0\n 70ns 0 1 0\n 75ns 1 0 0\n 80ns 1 0 0\n 85ns 1 1 1\n 90ns 1 1 1\n\nmodule TopModule (\n input a,\n input b,\n output q\n);\n\n", + "metadata": { + "file_size": 1217, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob090_circuit1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_355", + "file": "Prob156_review2015_fancytimer_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input wire clk,\n input wire reset,\n input wire data,\n output wire [3:0] count,\n output reg counting,\n output reg done,\n input wire ack\n);\n", + "metadata": { + "file_size": 166, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob156_review2015_fancytimer_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_356", + "file": "Prob027_fadd_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input cin,\n output cout,\n output sum\n);\n", + "metadata": { + "file_size": 86, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob027_fadd_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_357", + "file": "Prob049_m2014_q4b_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement a D flip flop, positive edge triggered, with an asynchronous\nreset \"ar\".\n\nmodule TopModule (\n input clk,\n input d,\n input ar,\n output logic q\n);\n\n", + "metadata": { + "file_size": 161, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob049_m2014_q4b_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_358", + "file": "Prob118_history_shift_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a 32-bit global history shift register, including support for\nrolling back state in response to a pipeline flush caused by a branch\nmisprediction. When a branch prediction is made (predict_valid = 1),\nshift in predict_taken from the LSB side to update the branch history for\nthe predicted branch. (predict_history[0] is the direction of the\nyoungest branch.) When a branch misprediction occurs (train_mispredicted\n= 1), load the branch history register with the history after the\ncompletion of the mispredicted branch. This is the history before the\nmispredicted branch (train_history) concatenated with the actual result\nof the branch (train_taken). If both a prediction and misprediction occur\nat the same time, the misprediction takes precedence, because the\npipeline flush will also flush out the branch that is currently making a\nprediction. predict_history is the value of the branch history register.\nareset is a positive edge triggered asynchronous reset that resets the\nhistory counter to zero.\n\nmodule TopModule (\n input clk,\n input areset,\n input predict_valid,\n input predict_taken,\n output logic [31:0] predict_history,\n\n input train_mispredicted,\n input train_taken,\n input [31:0] train_history\n);\n\n", + "metadata": { + "file_size": 1228, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob118_history_shift_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_359", + "file": "Prob078_dualedge_prompt.txt", + "task_type": "code_completion", + "content": "\nA dual-edge triggered flip-flop is triggered on both edges of the clock.\nHowever, FPGAs don't have dual-edge triggered flip-flops, and always\n@(posedge clk or negedge clk) is not accepted as a legal sensitivity\nlist. Build a circuit that functionally behaves like a dual-edge\ntriggered flip-flop.\n\nmodule TopModule (\n input clk,\n input d,\n output reg q\n);\n\n", + "metadata": { + "file_size": 361, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob078_dualedge_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_360", + "file": "Prob147_circuit10_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input a,\n input b,\n output q,\n output state\n);\n", + "metadata": { + "file_size": 85, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob147_circuit10_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_361", + "file": "Prob094_gatesv_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [3:0] in,\n output [2:0] out_both,\n output [3:1] out_any,\n output [3:0] out_different\n);\n", + "metadata": { + "file_size": 119, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob094_gatesv_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_362", + "file": "Prob004_vector2_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a circuit that reverses the byte order of a 32-bit vector.\n\nmodule TopModule (\n input [31:0] in,\n output [31:0] out\n);\n\n", + "metadata": { + "file_size": 129, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob004_vector2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_363", + "file": "Prob003_step_one_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a circuit with no inputs and one output. That output should always\ndrive 1 (or logic high).\n\nmodule TopModule (\n output one\n);\n\n", + "metadata": { + "file_size": 136, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob003_step_one_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_364", + "file": "Prob064_vector3_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [4:0] a,\n input [4:0] b,\n input [4:0] c,\n input [4:0] d,\n input [4:0] e,\n input [4:0] f,\n output [7:0] w,\n output [7:0] x,\n output [7:0] y,\n output [7:0] z\n);\n", + "metadata": { + "file_size": 196, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob064_vector3_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_365", + "file": "Prob018_mux256to1_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed\ninto a single 256-bit input vector. sel=0 should select in[0], sel=1\nselects bits in[1], sel=2 selects bits in[2], etc.\n\nmodule TopModule (\n input [255:0] in,\n input [7:0] sel,\n output out\n);\n\n", + "metadata": { + "file_size": 271, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob018_mux256to1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_366", + "file": "Prob012_xnorgate_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a module that implements an XNOR gate.\n\nmodule TopModule (\n input a,\n input b,\n output out\n);\n\n", + "metadata": { + "file_size": 106, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob012_xnorgate_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_367", + "file": "Prob141_count_clock_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n input ena,\n output reg pm,\n output reg [7:0] hh,\n output reg [7:0] mm,\n output reg [7:0] ss\n);\n", + "metadata": { + "file_size": 149, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob141_count_clock_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_368", + "file": "Prob062_bugs_mux2_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input sel,\n input [7:0] a,\n input [7:0] b,\n output reg [7:0] out\n);\n", + "metadata": { + "file_size": 93, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob062_bugs_mux2_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_369", + "file": "Prob105_rotate100_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input load,\n input [1:0] ena,\n input [99:0] data,\n output reg [99:0] q\n);\n", + "metadata": { + "file_size": 112, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob105_rotate100_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_370", + "file": "Prob027_fadd_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a full adder. A full adder adds three bits (including carry-in)\nand produces a sum and carry-out.\n\nmodule TopModule (\n input a,\n input b,\n input cin,\n output cout,\n output sum\n);\n\n", + "metadata": { + "file_size": 193, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob027_fadd_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_371", + "file": "Prob020_mt2015_eq2_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [1:0] A,\n input [1:0] B,\n output z\n);\n", + "metadata": { + "file_size": 68, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob020_mt2015_eq2_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_372", + "file": "Prob117_circuit9_prompt.txt", + "task_type": "code_completion", + "content": "\nThis is a sequential circuit. Read the simulation waveforms to determine\nwhat the circuit does, then implement it.\n\n time clk a q\n 0ns 0 1 x\n 5ns 1 1 4\n 10ns 0 1 4\n 15ns 1 1 4\n 20ns 0 1 4\n 25ns 1 1 4\n 30ns 0 1 4\n 35ns 1 1 4\n 40ns 0 1 4\n 45ns 1 0 4\n 50ns 0 0 4\n 55ns 1 0 5\n 60ns 0 0 5\n 65ns 1 0 6\n 70ns 0 0 6\n 75ns 1 0 0\n 80ns 0 0 0\n 85ns 1 0 1\n 90ns 0 0 1\n\nmodule TopModule (\n input clk,\n input a,\n output reg [2:0] q\n);\n\n", + "metadata": { + "file_size": 546, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob117_circuit9_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_373", + "file": "Prob106_always_nolatches_prompt.txt", + "task_type": "code_completion", + "content": "\nSuppose you're building a circuit to process scancodes from a PS/2\nkeyboard for a game. Given the last two bytes of scancodes received, you\nneed to indicate whether one of the arrow keys on the keyboard have been\npressed. This involves a fairly simple mapping, which can be implemented\nas a case statement (or if-elseif) with four cases.\n\n Scancode[15:0] | Arrow key\n 16'he06b | left arrow\n 16'he072 | down arrow\n 16'he074 | right arrow\n 16'he075 | up arrow\n Anything else | none\n\nYour circuit has one 16-bit input, and four outputs. Build this circuit\nthat recognizes these four scancodes and asserts the correct output.\n\nmodule TopModule (\n input [15:0] scancode,\n output reg left,\n output reg down,\n output reg right,\n output reg up\n);\n\n", + "metadata": { + "file_size": 777, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob106_always_nolatches_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_374", + "file": "Prob153_gshare_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a gshare branch predictor with 7-bit pc and 7-bit global history,\nhashed (using xor) into a 7-bit index. This index accesses a 128-entry\ntable of two-bit saturating counters. The branch predictor should contain\na 7-bit global branch history register. The branch predictor has two sets\nof interfaces: One for doing predictions and one for doing training. The\nprediction interface is used in the processor's Fetch stage to ask the\nbranch predictor for branch direction predictions for the instructions\nbeing fetched. Once these branches proceed down the pipeline and are\nexecuted, the true outcomes of the branches become known. The branch\npredictor is then trained using the actual branch direction outcomes.\n\nWhen a branch prediction is requested (predict_valid = 1) for a given pc,\nthe branch predictor produces the predicted branch direction and state of\nthe branch history register used to make the prediction. The branch\nhistory register is then updated (at the next positive clock edge) for\nthe predicted branch.\n\nWhen training for a branch is requested (train_valid = 1), the branch\npredictor is told the pc and branch history register value for the branch\nthat is being trained, as well as the actual branch outcome and whether\nthe branch was a misprediction (needing a pipeline flush). Update the\npattern history table (PHT) to train the branch predictor to predict this\nbranch more accurately next time. In addition, if the branch being\ntrained is mispredicted, also recover the branch history register to the\nstate immediately after the mispredicting branch completes execution.\n\nIf training for a misprediction and a prediction (for a different,\nyounger instruction) occurs in the same cycle, both operations will want\nto modify the branch history register. When this happens, training takes\nprecedence, because the branch being predicted will be discarded anyway.\nIf training and prediction of the same PHT entry happen at the same time,\nthe prediction sees the PHT state before training because training only\nmodifies the PHT at the next positive clock edge. The following timing\ndiagram shows the timing when training and predicting PHT entry 0 at the\nsame time. The training request at cycle 4 changes the PHT entry state in\ncycle 5, but the prediction request in cycle 4 outputs the PHT state at\ncycle 4, without considering the effect of the training request in cycle\n4. Reset is asynchronous active-high.\n\nmodule TopModule (\n input clk,\n input areset,\n\n input predict_valid,\n input [6:0] predict_pc,\n output predict_taken,\n output [6:0] predict_history,\n\n input train_valid,\n input train_taken,\n input train_mispredicted,\n input [6:0] train_history,\n input [6:0] train_pc\n);\n\n", + "metadata": { + "file_size": 2712, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob153_gshare_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_375", + "file": "Prob002_m2014_q4i_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n output out\n);\n", + "metadata": { + "file_size": 36, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob002_m2014_q4i_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_376", + "file": "Prob085_shift4_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a 4-bit shift register (right shift), with asynchronous positive\nedge triggered areset, synchronous active high signals load, and enable.\n\n (1) areset: Resets shift register to zero.\n\n (2) load: Loads shift register with data[3:0] instead of shifting.\n\n (3) ena: Shift right (q[3] becomes zero, q[0] is shifted out and\n disappears).\n\n (4) q: The contents of the shift register. If both the load and ena\n inputs are asserted (1), the load input has higher priority.\n\nmodule TopModule (\n input clk,\n input areset,\n input load,\n input ena,\n input [3:0] data,\n output reg [3:0] q\n);\n\n", + "metadata": { + "file_size": 609, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob085_shift4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_377", + "file": "Prob024_hadd_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n output sum,\n output cout\n);\n", + "metadata": { + "file_size": 73, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob024_hadd_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_378", + "file": "Prob022_mux2to1_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When\nsel=1, choose b.\n\nmodule TopModule (\n input a,\n input b,\n input sel,\n output out\n);\n\n", + "metadata": { + "file_size": 160, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob022_mux2to1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_379", + "file": "Prob153_gshare_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input areset,\n\n input predict_valid,\n input [6:0] predict_pc,\n output predict_taken,\n output [6:0] predict_history,\n\n input train_valid,\n input train_taken,\n input train_mispredicted,\n input [6:0] train_history,\n input [6:0] train_pc\n);\n", + "metadata": { + "file_size": 281, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob153_gshare_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_380", + "file": "Prob040_count10_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a decade counter that counts from 0 through 9, inclusive, with a\nperiod of 10. The reset input is active high synchronous, and should\nreset the counter to 0.\n\nmodule TopModule (\n input clk,\n input reset,\n output reg [3:0] q\n);\n\n", + "metadata": { + "file_size": 238, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob040_count10_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_381", + "file": "Prob146_fsm_serialdata_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input in,\n input reset,\n output [7:0] out_byte,\n output done\n);\n", + "metadata": { + "file_size": 102, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob146_fsm_serialdata_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_382", + "file": "Prob102_circuit3_prompt.txt", + "task_type": "code_completion", + "content": "\nThis is a combinational circuit. Read the simulation waveforms to\ndetermine what the circuit does, then implement it.\n\n time a b c d q\n 0ns 0 0 0 0 0\n 5ns 0 0 0 0 0\n 10ns 0 0 0 0 0\n 15ns 0 0 0 0 0\n 20ns 0 0 0 1 0\n 25ns 0 0 1 0 0\n 30ns 0 0 1 1 0\n 35ns 0 1 0 0 0\n 40ns 0 1 0 1 1\n 45ns 0 1 1 0 1\n 50ns 0 1 1 1 1\n 55ns 1 0 0 0 0\n 60ns 1 0 0 1 1\n 65ns 1 0 1 0 1\n 70ns 1 0 1 1 1\n 75ns 1 1 0 0 0\n 80ns 1 1 0 1 1\n 85ns 1 1 1 0 1\n 90ns 1 1 1 1 1\n\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output q\n);\n\n", + "metadata": { + "file_size": 639, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob102_circuit3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_383", + "file": "Prob026_alwaysblock1_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild an AND gate using both an assign statement and a combinational\nalways block.\n\nmodule TopModule (\n input a,\n input b,\n output out_assign,\n output reg out_alwaysblock\n);\n\n", + "metadata": { + "file_size": 180, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob026_alwaysblock1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_384", + "file": "Prob058_alwaysblock2_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input a,\n input b,\n output out_assign,\n output reg out_always_comb,\n output reg out_always_ff\n);\n", + "metadata": { + "file_size": 136, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob058_alwaysblock2_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_385", + "file": "Prob121_2014_q3bfsm_prompt.txt", + "task_type": "code_completion", + "content": "\nGiven the state-assigned table shown below, implement the finite-state\nmachine. Reset should synchronous active high reset the FSM to state 000.\n\n Present state y[2:0] | Next state y[2:0] x=0, Next state y[2:0] x=1 | Output z\n 000 | 000, 001 | 0\n 001 | 001, 100 | 0\n 010 | 010, 001 | 0\n 011 | 001, 010 | 1\n 100 | 011, 100 | 1\n\nmodule TopModule (\n input clk,\n input reset,\n input x,\n output reg z\n);\n\n", + "metadata": { + "file_size": 411, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob121_2014_q3bfsm_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_386", + "file": "Prob106_always_nolatches_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [15:0] scancode,\n output reg left,\n output reg down,\n output reg right,\n output reg up\n);\n", + "metadata": { + "file_size": 122, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob106_always_nolatches_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_387", + "file": "Prob089_ece241_2014_q5a_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input areset,\n input x,\n output z\n);\n", + "metadata": { + "file_size": 74, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob089_ece241_2014_q5a_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_388", + "file": "Prob037_review2015_count1k_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n output reg [9:0] q\n);\n", + "metadata": { + "file_size": 72, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob037_review2015_count1k_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_389", + "file": "Prob092_gatesv100_prompt.txt", + "task_type": "code_completion", + "content": "\nYou are given a 100-bit input vector in[99:0]. We want to know some\nrelationships between each bit and its neighbour:\n\n (1) out_both: Each bit of this output vector should indicate whether\n both the corresponding input bit and its neighbour to the left are '1'.\n For example, out_both[98] should indicate if in[98] and in[99] are both\n 1. Since in[99] has no neighbour to the left, the answer is obvious so\n we don't need to know out_both[99].\n\n (2) out_any: Each bit of this output vector should indicate whether any\n of the corresponding input bit and its neighbour to the right are '1'.\n For example, out_any[2] should indicate if either in[2] or in[1] are 1.\n Since in[0] has no neighbour to the right, the answer is obvious so we\n don't need to know out_any[0].\n\n (3) out_different: Each bit of this output vector should indicate\n whether the corresponding input bit is different from its neighbour to\n the left. For example, out_different[98] should indicate if in[98] is\n different from in[99]. For this part, treat the vector as wrapping\n around, so in[99]'s neighbour to the left is in[0].\n\nmodule TopModule (\n input [99:0] in,\n output [98:0] out_both,\n output [99:1] out_any,\n output [99:0] out_different\n);\n\n", + "metadata": { + "file_size": 1239, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob092_gatesv100_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_390", + "file": "Prob095_review2015_fsmshift_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n output shift_ena\n);\n", + "metadata": { + "file_size": 70, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob095_review2015_fsmshift_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_391", + "file": "Prob032_vector0_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a circuit that has one 3-bit input, then outputs the same vector,\nand also splits it into three separate 1-bit outputs. Connect output o0\nto the input vector's position 0, o1 to position 1, etc.\n\nmodule TopModule (\n input [2:0] vec,\n output [2:0] outv,\n output o2,\n output o1,\n output o0\n);\n\n", + "metadata": { + "file_size": 304, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob032_vector0_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_392", + "file": "Prob103_circuit2_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output q\n);\n", + "metadata": { + "file_size": 78, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob103_circuit2_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_393", + "file": "Prob138_2012_q2fsm_prompt.txt", + "task_type": "code_completion", + "content": "\nConsider the state machine shown below:\n\n A (0) --1--> B\n A (0) --0--> A\n B (0) --1--> C\n B (0) --0--> D\n C (0) --1--> E\n C (0) --0--> D\n D (0) --1--> F\n D (0) --0--> A\n E (1) --1--> E\n E (1) --0--> D\n F (1) --1--> C\n F (1) --0--> D\n\nReset resets into state A and is synchronous active-high.\n\nWrite complete Verilog code that represents this FSM. Use separate\n**always** blocks for the state table and the state flip-flops. Describe\nthe FSM output, which is called _z_, using either continuous assignment\nstatement(s) or an **always** block (at your discretion). Assign any\nstate codes that you wish to use.\n\nmodule TopModule (\n input clk,\n input reset,\n input w,\n output z\n);\n\n", + "metadata": { + "file_size": 695, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob138_2012_q2fsm_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_394", + "file": "Prob076_always_case_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a 6-to-1 multiplexer. When sel is between 0 and 5, choose the\ncorresponding data input. Otherwise, output 0. The data inputs and\noutputs are all 4 bits wide.\n\nmodule TopModule (\n input [2:0] sel,\n input [3:0] data0,\n input [3:0] data1,\n input [3:0] data2,\n input [3:0] data3,\n input [3:0] data4,\n input [3:0] data5,\n output reg [3:0] out\n);\n\n", + "metadata": { + "file_size": 358, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob076_always_case_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_395", + "file": "Prob044_vectorgates_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [2:0] a,\n input [2:0] b,\n output [2:0] out_or_bitwise,\n output out_or_logical,\n output [5:0] out_not\n);\n", + "metadata": { + "file_size": 136, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob044_vectorgates_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_396", + "file": "Prob102_circuit3_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output q\n);\n", + "metadata": { + "file_size": 78, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob102_circuit3_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_397", + "file": "Prob053_m2014_q4d_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement in Verilog the following circuit: A D flip-flop takes as input\nthe output of a two-input XOR. The flip-flop is positive edge triggered\nby clk, but there is no reset. The XOR takes as input 'in' along with the\noutput 'out' of the flip-flop.\n\nmodule TopModule (\n input clk,\n input in,\n output logic out\n);\n\n", + "metadata": { + "file_size": 319, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob053_m2014_q4d_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_398", + "file": "Prob042_vector4_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [7:0] in,\n output [31:0] out\n);\n", + "metadata": { + "file_size": 61, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob042_vector4_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_399", + "file": "Prob021_mux256to1v_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [1023:0] in,\n input [7:0] sel,\n output [3:0] out\n);\n", + "metadata": { + "file_size": 82, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob021_mux256to1v_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_400", + "file": "Prob116_m2014_q3_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [4:1] x,\n output logic f\n);\n", + "metadata": { + "file_size": 57, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob116_m2014_q3_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_401", + "file": "Prob120_fsm3s_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input in,\n input reset,\n output out\n);\n", + "metadata": { + "file_size": 76, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob120_fsm3s_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_402", + "file": "Prob063_review2015_shiftcount_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a four-bit shift register that also acts as a down counter. Data is\nshifted in most-significant-bit first when shift_ena is 1. The number\ncurrently in the shift register is decremented when count_ena is 1. Since\nthe full system doesn't ever use shift_ena and count_ena together, it\ndoes not matter what your circuit does if both control inputs are 1 (This\nmainly means that it doesn't matter which case gets higher priority).\n\nmodule TopModule (\n input clk,\n input shift_ena,\n input count_ena,\n input data,\n output reg [3:0] q\n);\n\n", + "metadata": { + "file_size": 543, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob063_review2015_shiftcount_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_403", + "file": "Prob142_lemmings2_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input areset,\n input bump_left,\n input bump_right,\n input ground,\n output walk_left,\n output walk_right,\n output aaah\n);\n", + "metadata": { + "file_size": 162, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob142_lemmings2_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_404", + "file": "Prob108_rule90_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input load,\n input [511:0] data,\n output reg [511:0] q\n);\n", + "metadata": { + "file_size": 95, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob108_rule90_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_405", + "file": "Prob028_m2014_q4a_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input d,\n input ena,\n output logic q\n);\n", + "metadata": { + "file_size": 64, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob028_m2014_q4a_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_406", + "file": "Prob036_ringer_prompt.txt", + "task_type": "code_completion", + "content": "\nSuppose you are designing a circuit to control a cellphone's ringer and\nvibration motor. Whenever the phone needs to ring from an incoming call\n(input ring), your circuit must either turn on the ringer (output ringer\n= 1) or the motor (output motor = 1), but not both. If the phone is in\nvibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn\non the ringer.\n\nmodule TopModule (\n input ring,\n input vibrate_mode,\n output ringer,\n output motor\n);\n\n", + "metadata": { + "file_size": 470, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob036_ringer_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_407", + "file": "Prob034_dff8_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input [7:0] d,\n output reg [7:0] q\n);\n", + "metadata": { + "file_size": 74, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob034_dff8_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_408", + "file": "Prob093_ece241_2014_q3_prompt.txt", + "task_type": "code_completion", + "content": "\nFor the following Karnaugh map, give the circuit implementation using one\n4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using\nas few as possible. You are not allowed to use any other logic gate and\nyou must use _a_ and _b_ as the multiplexer selector inputs, as shown on\nthe 4-to-1 multiplexer below.\n\n ab\n cd 00 01 11 10\n 00 | 0 | 0 | 0 | 1 |\n 01 | 1 | 0 | 0 | 0 |\n 11 | 1 | 0 | 1 | 1 |\n 10 | 1 | 0 | 0 | 1 |\n\nConsider a block diagram with inputs 'c' and 'd' going into a module\ncalled \"top_module\". This \"top_module\" has four outputs, mux_in[3:0],\nthat connect to a four input mux. The mux takes as input {a,b} and ab =\n00 is connected to mux_in[0], ab=01 is connected to mux_in[1], and so in.\nYou are implementing in Verilog just the portion labelled \"top_module\",\nsuch that the entire circuit (including the 4-to-1 mux) implements the\nK-map.\n\nmodule TopModule (\n input c,\n input d,\n output [3:0] mux_in\n);\n\n", + "metadata": { + "file_size": 951, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob093_ece241_2014_q3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_409", + "file": "Prob146_fsm_serialdata_prompt.txt", + "task_type": "code_completion", + "content": "\nIn many (older) serial communications protocols, each data byte is sent\nalong with a start bit and a stop bit, to help the receiver delimit bytes\nfrom the stream of bits. One common scheme is to use one start bit (0), 8\ndata bits, and 1 stop bit (1). The line is also at logic 1 when nothing\nis being transmitted (idle). Design a finite state machine that will\nidentify when bytes have been correctly received when given a stream of\nbits. It needs to identify the start bit, wait for all 8 data bits, then\nverify that the stop bit was correct. The module will also output the\ncorrectly- received data byte. out_byte needs to be valid when done is 1,\nand is don't-care otherwise.If the stop bit does not appear when\nexpected, the FSM must wait until it finds a stop bit before attempting\nto receive the next byte. Include a active-high synchronous reset. Note\nthat the serial protocol sends the least significant bit first. It should\nassert done each time it finds a stop bit.\n\nmodule TopModule (\n input clk,\n input in,\n input reset,\n output [7:0] out_byte,\n output done\n);\n\n", + "metadata": { + "file_size": 1080, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob146_fsm_serialdata_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_410", + "file": "Prob049_m2014_q4b_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input d,\n input ar,\n output logic q\n);\n", + "metadata": { + "file_size": 76, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob049_m2014_q4b_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_411", + "file": "Prob054_edgedetect_prompt.txt", + "task_type": "code_completion", + "content": "\nFor each bit in an 8-bit vector, detect when the input signal changes\nfrom 0 in one clock cycle to 1 the next (similar to positive edge\ndetection). The output bit should be set the cycle after a 0 to 1\ntransition occurs.\n\nmodule TopModule (\n input clk,\n input [7:0] in,\n output reg [7:0] pedge\n);\n\n", + "metadata": { + "file_size": 302, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob054_edgedetect_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_412", + "file": "Prob019_m2014_q4f_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement the following circuit in Verilog. Two inputs (in1 and in2) go\nto an AND gate, but the in2 input to the AND gate has a bubble. The\noutput of the AND gate is connected to 'out'.\n\nmodule TopModule (\n input in1,\n input in2,\n output logic out\n);\n\n", + "metadata": { + "file_size": 256, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob019_m2014_q4f_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_413", + "file": "Prob101_circuit4_prompt.txt", + "task_type": "code_completion", + "content": "\nThis is a combinational circuit. Read the simulation waveforms to\ndetermine what the circuit does, then implement it.\n\n time a b c d q\n 0ns 0 0 0 0 0\n 5ns 0 0 0 0 0\n 10ns 0 0 0 0 0\n 15ns 0 0 0 0 0\n 20ns 0 0 0 1 0\n 25ns 0 0 1 0 1\n 30ns 0 0 1 1 1\n 35ns 0 1 0 0 1\n 40ns 0 1 0 1 1\n 45ns 0 1 1 0 1\n 50ns 0 1 1 1 1\n 55ns 1 0 0 0 0\n 60ns 1 0 0 1 0\n 65ns 1 0 1 0 1\n 70ns 1 0 1 1 1\n 75ns 1 1 0 0 1\n 80ns 1 1 0 1 1\n 85ns 1 1 1 0 1\n 90ns 1 1 1 1 1\n\nmodule TopModule (\n input a,\n input b,\n input c,\n input d,\n output q\n);\n\n", + "metadata": { + "file_size": 639, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob101_circuit4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_414", + "file": "Prob056_ece241_2013_q7_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input j,\n input k,\n output reg Q\n);\n", + "metadata": { + "file_size": 73, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob056_ece241_2013_q7_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_415", + "file": "Prob109_fsm1_prompt.txt", + "task_type": "code_completion", + "content": "\nConsider the follow Moore machine with the diagram described below:\n\n B (1) --0--> A\n B (1) --1--> B\n A (0) --0--> B\n A (0) --1--> A\n\nWrite Verilog implementing this state machine. It should asynchronously\nreset into state B if reset if high.\n\nmodule TopModule (\n input clk,\n input in,\n input areset,\n output out\n);\n\n", + "metadata": { + "file_size": 326, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob109_fsm1_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_416", + "file": "Prob111_fsm2s_prompt.txt", + "task_type": "code_completion", + "content": "\nThis is a Moore state machine with two states, two inputs, and one\noutput. Implement this state machine in Verilog. Reset is an active-high\nsynchronous reset to state OFF.\n\n OFF (out=0) --j=0--> OFF\n OFF (out=0) --j=1--> ON\n ON (out=1) --k=0--> ON\n ON (out=1) --k=1--> OFF\n\nmodule TopModule (\n input clk,\n input j,\n input k,\n input reset,\n output out\n);\n\n", + "metadata": { + "file_size": 367, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob111_fsm2s_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_417", + "file": "Prob117_circuit9_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input a,\n output reg [2:0] q\n);\n", + "metadata": { + "file_size": 68, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob117_circuit9_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_418", + "file": "Prob119_fsm3_prompt.txt", + "task_type": "code_completion", + "content": "\nThe following is the state transition table for a Moore state machine\nwith one input, one output, and four states. Implement this state\nmachine. Include a positive edge triggered asynchronous reset that resets\nthe FSM to state A.\n\n state | next state in=0, next state in=1 | output\n A | A, B | 0\n B | C, B | 0\n C | A, D | 0\n D | C, B | 1\n\nmodule TopModule (\n input clk,\n input in,\n input areset,\n output out\n);\n\n", + "metadata": { + "file_size": 550, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob119_fsm3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_419", + "file": "Prob073_dff16e_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input resetn,\n input [1:0] byteena,\n input [15:0] d,\n output reg [15:0] q\n);\n", + "metadata": { + "file_size": 115, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob073_dff16e_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_420", + "file": "Prob029_m2014_q4g_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement in Verilog the following circuit: A two-input XNOR (connected\nto 'in1' and 'in2) has an output connected to the input of a two-input\nXOR. The second input of the XOR is 'in3.' The output of the XOR is\n'out'.\n\nmodule TopModule (\n input in1,\n input in2,\n input in3,\n output logic out\n);\n\n", + "metadata": { + "file_size": 301, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob029_m2014_q4g_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_421", + "file": "Prob154_fsm_ps2data_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input [7:0] in,\n input reset,\n output [23:0] out_bytes,\n output done\n);\n", + "metadata": { + "file_size": 110, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob154_fsm_ps2data_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_422", + "file": "Prob137_fsm_serial_prompt.txt", + "task_type": "code_completion", + "content": "\nIn many (older) serial communications protocols, each data byte is sent\nalong with a start bit and a stop bit, to help the receiver delimit bytes\nfrom the stream of bits. One common scheme is to use one start bit (0), 8\ndata bits, and 1 stop bit (1). The line is also at logic 1 when nothing\nis being transmitted (idle). Design a finite state machine that will\nidentify when bytes have been correctly received when given a stream of\nbits. It needs to identify the start bit, wait for all 8 data bits, then\nverify that the stop bit was correct. If the stop bit does not appear\nwhen expected, the FSM must wait until it finds a stop bit before\nattempting to receive the next byte. Include a active-high synchronous\nreset. Note that the serial protocol sends the least significant bit\nfirst.\n\nmodule TopModule (\n input clk,\n input in,\n input reset,\n output done\n);\n\n", + "metadata": { + "file_size": 868, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob137_fsm_serial_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_423", + "file": "Prob005_notgate_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input in,\n output out\n);\n", + "metadata": { + "file_size": 48, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob005_notgate_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_424", + "file": "Prob060_m2014_q4k_prompt.txt", + "task_type": "code_completion", + "content": "\nImplement a shift register with four D flops. Reset is active-low\nsynchronous resettable.\n\nmodule TopModule (\n input clk,\n input resetn,\n input in,\n output out\n);\n\n", + "metadata": { + "file_size": 169, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob060_m2014_q4k_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_425", + "file": "Prob039_always_if_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a 2-to-1 mux that chooses between a and b. Choose b if both sel_b1\nand sel_b2 are true. Otherwise, choose a. Do the same twice, once using\nassign statements and once using a procedural if statement.\n\nmodule TopModule (\n input a,\n input b,\n input sel_b1,\n input sel_b2,\n output out_assign,\n output reg out_always\n);\n\n", + "metadata": { + "file_size": 329, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob039_always_if_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_426", + "file": "Prob068_countbcd_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n output [3:1] ena,\n output reg [15:0] q\n);\n", + "metadata": { + "file_size": 93, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob068_countbcd_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_427", + "file": "Prob142_lemmings2_prompt.txt", + "task_type": "code_completion", + "content": "\nThe game Lemmings involves critters with fairly simple brains. So simple\nthat we are going to model it using a finite state machine. In the\nLemmings' 2D world, Lemmings can be in one of two states: walking left\n(walk_left is 1) or walking right (walk_right is 1). It will switch\ndirections if it hits an obstacle. In particular, if a Lemming is bumped\non the left (by receiving a 1 on bump_left), it will walk right. If it's\nbumped on the right (by receiving a 1 on bump_right), it will walk left.\nIf it's bumped on both sides at the same time, it will still switch\ndirections.\n\nIn addition to walking left and right and changing direction when bumped,\nwhen ground=0, the Lemming will fall and say \"aaah!\". When the ground\nreappears (ground=1), the Lemming will resume walking in the same\ndirection as before the fall. Being bumped while falling does not affect\nthe walking direction, and being bumped in the same cycle as ground\ndisappears (but not yet falling), or when the ground reappears while\nstill falling, also does not affect the walking direction.\n\nImplement a Moore state machine that models this behaviour. areset is\npositive edge triggered asynchronous reseting the Lemming machine to walk\nleft.\n\nmodule TopModule (\n input clk,\n input areset,\n input bump_left,\n input bump_right,\n input ground,\n output walk_left,\n output walk_right,\n output aaah\n);\n\n", + "metadata": { + "file_size": 1373, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob142_lemmings2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_428", + "file": "Prob051_gates4_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [3:0] in,\n output out_and,\n output out_or,\n output out_xor\n);\n", + "metadata": { + "file_size": 93, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob051_gates4_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_429", + "file": "Prob151_review2015_fsm_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n input data,\n output reg shift_ena,\n output reg counting,\n input done_counting,\n output reg done,\n input ack\n);\n", + "metadata": { + "file_size": 166, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob151_review2015_fsm_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_430", + "file": "Prob041_dff8r_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate 8 D flip-flops with active high synchronous reset setting the\noutput to zero. All DFFs should be triggered by the positive edge of clk.\n\nmodule TopModule (\n input clk,\n input [7:0] d,\n input reset,\n output reg [7:0] q\n);\n\n", + "metadata": { + "file_size": 234, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob041_dff8r_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_431", + "file": "Prob155_lemmings4_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input areset,\n input bump_left,\n input bump_right,\n input ground,\n input dig,\n output walk_left,\n output walk_right,\n output aaah,\n output digging\n);\n", + "metadata": { + "file_size": 193, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob155_lemmings4_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_432", + "file": "Prob048_m2014_q4c_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input d,\n input r,\n output logic q\n);\n", + "metadata": { + "file_size": 75, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob048_m2014_q4c_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_433", + "file": "Prob105_rotate100_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a 100-bit left/right rotator, with synchronous load and left/right\nenable. A rotator shifts-in the shifted-out bit from the other end of the\nregister, unlike a shifter that discards the shifted-out bit and shifts\nin a zero. If enabled, a rotator rotates the bits around and does not\nmodify/discard them.\n\n (1) load: Loads shift register with data[99:0] instead of rotating.\n Synchronous active high.\n\n (2) ena[1:0]: Synchronous. Chooses whether and which direction to\n rotate:\n (a) 2'b01 rotates right by one bit,\n (b) 2'b10 rotates left by one bit,\n (c) 2'b00 and 2'b11 do not rotate.\n\n (3) q: The contents of the rotator.\n\nmodule TopModule (\n input clk,\n input load,\n input [1:0] ena,\n input [99:0] data,\n output reg [99:0] q\n);\n\n", + "metadata": { + "file_size": 772, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob105_rotate100_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_434", + "file": "Prob150_review2015_fsmonehot_prompt.txt", + "task_type": "code_completion", + "content": "\nGiven the following Moore state machine with 3 input (d, done_counting,\nack) and 3 outputs (shift_ena, counting, done). Unless otherwise stated in\nthe diagram below, assume outputs are 0 and inputs are don't cares.\n\nstate (output) --input--> next state\n-------------------------------------------\n S () --d=0--> S\n S () --d=1--> S1\n S1 () --d=0--> S\n S1 () --d=1--> S11\n S11 () --d=0--> S110\n S11 () --d=1--> S11\n S110 () --d=0--> S\n S110 () --d=1--> B0\n B0 (shift_ena=1) --(always go to next cycle)--> B1\n B1 (shift_ena=1) --(always go to next cycle)--> B2\n B2 (shift_ena=1) --(always go to next cycle)--> B3\n B3 (shift_ena=1) --(always go to next cycle)--> Count\n Count (counting=1) --done_counting=0--> Count\n Count (counting=1) --done_counting=1--> Wait\n Wait (done=1) --ack=0--> Wait\n Wait (done=1) --ack=1--> S\n\nAt reset, the state machine starts in state \"S\". Derive next-state logic\nequations and output logic equations by inspection assuming the following\none-hot encoding is used: (S, S1, S11, S110, B0, B1, B2, B3, Count, Wait)\n= (10'b0000000001, 10'b0000000010, 10'b0000000100, ... , 10'b1000000000)\n\nDerive state transition and output logic equations by inspection assuming\na one-hot encoding. Implement only the state transition logic and output\nlogic (the combinational logic portion) for this state machine.\n\nWrite code that generates the following signals:\n\n - B3_next -- Assert when next-state is B3 state\n - S_next -- Assert when next-state is S state\n - S1_next -- Assert when next-state is S1 state\n - Count_next -- Assert when next-state is Count state\n - Wait_next -- Assert when next-state is Wait state\n - done -- output logic\n - counting -- output logic\n - shift_ena -- output logic\n\nmodule TopModule (\n input d,\n input done_counting,\n input ack,\n input [9:0] state, // 10-bit one-hot current state\n output B3_next,\n output S_next,\n output S1_next,\n output Count_next,\n output Wait_next,\n output done,\n output counting,\n output shift_ena\n);\n\n", + "metadata": { + "file_size": 2138, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob150_review2015_fsmonehot_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_435", + "file": "Prob154_fsm_ps2data_prompt.txt", + "task_type": "code_completion", + "content": "\nWe want a finite state machine that will search for message boundaries\nwhen given an input byte stream. The algorithm we'll use is to discard\nbytes until we see one with in[3]=1. We then assume that this is byte 1\nof a message, and signal the receipt of a message once all 3 bytes have\nbeen received (done). The FSM should signal done in the cycle immediately\nafter the third byte of each message was successfully received.\n\nImplement the datapath module that will output the 24-bit (3 byte)\nmessage whenever a packet is received (out_bytes[23:16] is the first\nbyte, out_bytes[15:8] is the second byte, etc.). The reset signal is\nactive high synchronous. out_bytes needs to be valid whenever the done\nsignal is asserted. You may output anything at other times (i.e.,\ndon't-care).\n\n Waveform example:\n time clk rst in done out_bytes\n 0ns 0 1 0 x x\n 5ns 1 1 0 0 x\n 10ns 0 1 0 0 x\n 15ns 1 0 2c 0 x\n 20ns 0 0 2c 0 x\n 25ns 1 0 81 0 x\n 30ns 0 0 81 0 x\n 35ns 1 0 9 0 x\n 40ns 0 0 9 0 x\n 45ns 1 0 6b 1 2c8109\n 50ns 0 0 6b 1 2c8109\n 55ns 1 0 d 0 x\n 60ns 0 0 d 0 x\n 65ns 1 0 8d 0 x\n 70ns 0 0 8d 0 x\n 75ns 1 0 6d 1 6b0d8d\n 80ns 0 0 6d 1 6b0d8d\n 85ns 1 0 12 0 x\n 90ns 0 0 12 0 x\n 95ns 1 0 1 0 x\n 100ns 0 0 1 0 x\n 105ns 1 0 d 1 6d1201\n 110ns 0 0 d 1 6d1201\n 115ns 1 0 76 0 x\n 120ns 0 0 76 0 x\n 125ns 1 0 3d 0 x\n 130ns 0 0 3d 0 x\n 135ns 1 0 ed 1 d763d\n 140ns 0 0 ed 1 d763d\n 145ns 1 0 8c 0 x\n 150ns 0 0 8c 0 x\n 155ns 1 0 f9 0 x\n 160ns 0 0 f9 0 x\n 165ns 1 0 ce 1 ed8cf9\n 170ns 0 0 ce 1 ed8cf9\n 175ns 1 0 c5 0 x\n 180ns 0 0 c5 0 x\n 185ns 1 0 aa 0 x\n 190ns 0 0 aa 0 x\n\nmodule TopModule (\n input clk,\n input [7:0] in,\n input reset,\n output [23:0] out_bytes,\n output done\n);\n\n", + "metadata": { + "file_size": 2236, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob154_fsm_ps2data_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_436", + "file": "Prob055_conditional_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [7:0] a,\n input [7:0] b,\n input [7:0] c,\n input [7:0] d,\n output reg [7:0] min\n);\n", + "metadata": { + "file_size": 114, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob055_conditional_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_437", + "file": "Prob096_review2015_fsmseq_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a finite-state machine that searches for the sequence 1101 in an\ninput bit stream. When the sequence is found, it should set\nstart_shifting to 1, forever, until reset. Reset is active high\nsynchronous.\n\nmodule TopModule (\n input clk,\n input reset,\n input data,\n output start_shifting\n);\n\n", + "metadata": { + "file_size": 299, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob096_review2015_fsmseq_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_438", + "file": "Prob132_always_if2_prompt.txt", + "task_type": "code_completion", + "content": "\nFix any and all bugs in this code:\n\n module top_module (\n input cpu_overheated,\n output reg shut_off_computer,\n input arrived,\n input gas_tank_empty,\n output reg keep_driving );\n\n always @(*) begin\n if (cpu_overheated)\n shut_off_computer = 1;\n end\n\n always @(*) begin\n if (~arrived)\n keep_driving = ~gas_tank_empty;\n end\n\n endmodule\n\nmodule TopModule (\n input cpu_overheated,\n output reg shut_off_computer,\n input arrived,\n input gas_tank_empty,\n output reg keep_driving\n);\n\n", + "metadata": { + "file_size": 586, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob132_always_if2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_439", + "file": "Prob038_count15_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a 4-bit binary counter that counts from 0 through 15, inclusive,\nwith a period of 16. The reset input is active high synchronous, and\nshould reset the counter to 0.\n\nmodule TopModule (\n input clk,\n input reset,\n output reg [3:0] q\n);\n\n", + "metadata": { + "file_size": 245, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob038_count15_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_440", + "file": "Prob032_vector0_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [2:0] vec,\n output [2:0] outv,\n output o2,\n output o1,\n output o0\n);\n", + "metadata": { + "file_size": 101, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob032_vector0_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_441", + "file": "Prob011_norgate_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a module that implements a NOR gate.\n\nmodule TopModule (\n input a,\n input b,\n output out\n);\n\n", + "metadata": { + "file_size": 104, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob011_norgate_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_442", + "file": "Prob020_mt2015_eq2_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a circuit that has two 2-bit inputs A[1:0] and B[1:0], and\nproduces an output z. The value of z should be 1 if A = B, otherwise z\nshould be 0.\n\nmodule TopModule (\n input [1:0] A,\n input [1:0] B,\n output z\n);\n\n", + "metadata": { + "file_size": 220, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob020_mt2015_eq2_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_443", + "file": "Prob059_wire4_prompt.txt", + "task_type": "code_completion", + "content": "\nCreate a module with 3 inputs and 4 outputs that behaves like wires that\nmakes these connections:\n\n a -> w\n b -> x\n b -> y\n c -> z\n\nmodule TopModule (\n input a,\n input b,\n input c,\n output w,\n output x,\n output y,\n output z\n);\n\n", + "metadata": { + "file_size": 240, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob059_wire4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_444", + "file": "Prob140_fsm_hdlc_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n input in,\n output disc,\n output flag,\n output err\n);\n", + "metadata": { + "file_size": 106, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob140_fsm_hdlc_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_445", + "file": "Prob134_2014_q3c_prompt.txt", + "task_type": "code_completion", + "content": "\nGiven the state-assigned table shown below, implement the logic functions\nY[0] and z.\n\n Present state input y[2:0] | Next state Y[2:0] when x=0, Next state Y[2:0] when x=1 | Output z\n 000 | 000, 001 | 0\n 001 | 001, 100 | 0\n 010 | 010, 001 | 0\n 011 | 001, 010 | 1\n 100 | 011, 100 | 1\n\nmodule TopModule (\n input clk,\n input x,\n input [2:0] y,\n output reg Y0,\n output reg z\n);\n\n", + "metadata": { + "file_size": 393, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob134_2014_q3c_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_446", + "file": "Prob061_2014_q4a_prompt.txt", + "task_type": "code_completion", + "content": "\nConsider an n-bit shift register circuit. Inputs E are for enabling\nshift, R for value to load, L is asserted when it should load, and w is\nthe input to the first stage of the shift register. Write a Verilog\nmodule named top_module for one stage of this circuit, including both the\nflip-flop and multiplexers.\n\nmodule TopModule (\n input clk,\n input w,\n input R,\n input E,\n input L,\n output reg Q\n);\n\n", + "metadata": { + "file_size": 407, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob061_2014_q4a_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_447", + "file": "Prob152_lemmings3_prompt.txt", + "task_type": "code_completion", + "content": "\nThe game Lemmings involves critters with fairly simple brains. So simple\nthat we are going to model it using a finite state machine. In the\nLemmings' 2D world, Lemmings can be in one of two states: walking left\n(walk_left is 1) or walking right (walk_right is 1). It will switch\ndirections if it hits an obstacle. In particular, if a Lemming is bumped\non the left (by receiving a 1 on bump_left), it will walk right. If it's\nbumped on the right (by receiving a 1 on bump_right), it will walk left.\nIf it's bumped on both sides at the same time, it will still switch\ndirections.\n\nIn addition to walking left and right and changing direction when bumped,\nwhen ground=0, the Lemming will fall and say \"aaah!\". When the ground\nreappears (ground=1), the Lemming will resume walking in the same\ndirection as before the fall. Being bumped while falling does not affect\nthe walking direction, and being bumped in the same cycle as ground\ndisappears (but not yet falling), or when the ground reappears while\nstill falling, also does not affect the walking direction.\n\nIn addition to walking and falling, Lemmings can sometimes be told to do\nuseful things, like dig (it starts digging when dig=1). A Lemming can dig\nif it is currently walking on ground (ground=1 and not falling), and will\ncontinue digging until it reaches the other side (ground=0). At that\npoint, since there is no ground, it will fall (aaah!), then continue\nwalking in its original direction once it hits ground again. As with\nfalling, being bumped while digging has no effect, and being told to dig\nwhen falling or when there is no ground is ignored. (In other words, a\nwalking Lemming can fall, dig, or switch directions. If more than one of\nthese conditions are satisfied, fall has higher precedence than dig,\nwhich has higher precedence than switching directions.)\n\nImplement a Moore state machine that models this behaviour. areset is\npositive edge triggered asynchronous reseting the Lemming machine to walk\nleft.\n\nmodule TopModule (\n input clk,\n input areset,\n input bump_left,\n input bump_right,\n input ground,\n input dig,\n output walk_left,\n output walk_right,\n output aaah,\n output digging\n);\n\n", + "metadata": { + "file_size": 2175, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob152_lemmings3_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_448", + "file": "Prob086_lfsr5_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n output reg [4:0] q\n);\n", + "metadata": { + "file_size": 72, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob086_lfsr5_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_449", + "file": "Prob115_shift18_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a 64-bit arithmetic shift register, with synchronous load. The\nshifter can shift both left and right, and by 1 or 8 bit positions,\nselected by \"amount.\" Assume the right shit is an arithmetic right shift.\n\nSignals are defined as below:\n\n (1) load: Loads shift register with data[63:0] instead of shifting.\n Active high.\n (2) ena: Chooses whether to shift. Active high.\n (3) amount: Chooses which direction and how much to shift.\n (a) 2'b00: shift left by 1 bit.\n (b) 2'b01: shift left by 8 bits.\n (c) 2'b10: shift right by 1 bit.\n (d) 2'b11: shift right by 8 bits.\n (4) q: The contents of the shifter.\n\nmodule TopModule (\n input clk,\n input load,\n input ena,\n input [1:0] amount,\n input [63:0] data,\n output reg [63:0] q\n);\n\n", + "metadata": { + "file_size": 768, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob115_shift18_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_450", + "file": "Prob072_thermostat_prompt.txt", + "task_type": "code_completion", + "content": "\nA heating/cooling thermostat controls both a heater (during winter) and\nan air conditioner (during summer). Implement a circuit that will turn on\nand off the heater, air conditioning, and blower fan as appropriate. The\nthermostat can be in one of two modes: heating (mode = 1) and cooling\n(mode = 0). In heating mode, turn the heater on when it is too cold\n(too_cold = 1) but do not use the air conditioner. In cooling mode, turn\nthe air conditioner on when it is too hot (too_hot = 1), but do not turn\non the heater. When the heater or air conditioner are on, also turn on\nthe fan to circulate the air. In addition, the user can also request the\nfan to turn on (fan_on = 1), even if the heater and air conditioner are\noff.\n\nmodule TopModule (\n input mode,\n input too_cold,\n input too_hot,\n input fan_on,\n output heater,\n output aircon,\n output fan\n);\n\n", + "metadata": { + "file_size": 861, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob072_thermostat_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_451", + "file": "Prob065_7420_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input p1a,\n input p1b,\n input p1c,\n input p1d,\n output p1y,\n input p2a,\n input p2b,\n input p2c,\n input p2d,\n output p2y\n);\n", + "metadata": { + "file_size": 154, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob065_7420_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_452", + "file": "Prob061_2014_q4a_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input w,\n input R,\n input E,\n input L,\n output reg Q\n);\n", + "metadata": { + "file_size": 95, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob061_2014_q4a_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_453", + "file": "Prob110_fsm2_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input j,\n input k,\n input areset,\n output out\n);\n", + "metadata": { + "file_size": 87, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob110_fsm2_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_454", + "file": "Prob089_ece241_2014_q5a_prompt.txt", + "task_type": "code_completion", + "content": "\nYou are to design a one-input one-output serial 2's complementer Moore\nstate machine. The input (x) is a series of bits (one per clock cycle)\nbeginning with the least-significant bit of the number, and the output\n(Z) is the 2's complement of the input. The machine will accept input\nnumbers of arbitrary length. The circuit requires a positive edge\ntriggered asynchronous reset. The conversion begins when Reset is\nreleased and stops when Reset is asserted.\n\nmodule TopModule (\n input clk,\n input areset,\n input x,\n output z\n);\n\n", + "metadata": { + "file_size": 534, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob089_ece241_2014_q5a_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_455", + "file": "Prob149_ece241_2013_q4_prompt.txt", + "task_type": "code_completion", + "content": "\nA large reservior of water serves several users. In order to keep the\nlevel of water succificently high, three sensors are placed vertically at\n5-inch intervals. When the water level is above the highest sensor s[3],\nthe input flow rate should be zero. When the level is below the lowest\nsensor s[1], the flow rate should be at maximum (both Nominal flow valve\nand Supplemental flow valve opened). The flow rate when the level is\nbetween the upper and lower sensors is determined by two factors: the\nwater level and the level previous to the last sensor change. Each water\nlevel has a nominal flow rate associated with it as show in the table\nbelow. If the sensor change indicates that the previous level was lower\nthan the current level, the flow rate should be increased by opening the\nSupplemental flow valve (controlled by dfr).\n\n Water Level | Sensors Asserted | Nominal Flow Rate Inputs to be Asserted\n Above s[3] | s[1], s[2], s[3] | None\n Between s[3] and s[2] | s[1], s[2] | fr1\n Between s[2] and s[1] | s[1] | fr1, fr2\n Below s[1] | None | fr1, fr2, fr3\n\nAlso include an active-high synchronous reset that resets the state\nmachine to a state equivalent to if the water level had been low for a\nlong time (no sensors asserted, and all four outputs asserted).\n\nmodule TopModule (\n input clk,\n input reset,\n input [3:1] s,\n output reg fr3,\n output reg fr2,\n output reg fr1,\n output reg dfr\n);\n\n", + "metadata": { + "file_size": 1476, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob149_ece241_2013_q4_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_456", + "file": "Prob068_countbcd_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is\nencoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit,\netc. For digits [3:1], also output an enable signal indicating when each\nof the upper three digits should be incremented. Include a synchronous\nactive-high reset.\n\nmodule TopModule (\n input clk,\n input reset,\n output [3:1] ena,\n output reg [15:0] q\n);\n\n", + "metadata": { + "file_size": 406, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob068_countbcd_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_457", + "file": "Prob136_m2014_q6_prompt.txt", + "task_type": "code_completion", + "content": "\nConsider the state machine shown below:\n\n A (0) --0--> B\n A (0) --1--> A\n B (0) --0--> C\n B (0) --1--> D\n C (0) --0--> E\n C (0) --1--> D\n D (0) --0--> F\n D (0) --1--> A\n E (1) --0--> E\n E (1) --1--> D\n F (1) --0--> C\n F (1) --1--> D\n\nImplement this state machine in Verilog.\n\nmodule TopModule (\n input clk,\n input reset,\n input w,\n output z\n);\n\n", + "metadata": { + "file_size": 362, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob136_m2014_q6_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_458", + "file": "Prob008_m2014_q4h_prompt.txt", + "task_type": "code_completion", + "content": "\nThe module assigns the output port to the same value as the input port\ncombinationally.\n\nmodule TopModule (\n input in,\n output out\n);\n\n", + "metadata": { + "file_size": 138, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob008_m2014_q4h_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_459", + "file": "Prob123_bugs_addsubz_prompt.txt", + "task_type": "code_completion", + "content": "\nThe following adder-subtractor with zero flag doesn't work. Fix the\nbug(s).\n\n synthesis verilog_input_version verilog_2001\n module top_module (\n input do_sub,\n input [7:0] a,\n input [7:0] b,\n output reg [7:0] out,\n output reg result_is_zero\n );\n\n always @(*) begin\n case (do_sub)\n 0: out = a+b;\n 1: out = a-b;\n endcase\n\n if (~out)\n result_is_zero = 1;\n end\n\n endmodule\n\nmodule TopModule (\n input do_sub,\n input [7:0] a,\n input [7:0] b,\n output reg [7:0] out,\n output reg result_is_zero\n);\n\n", + "metadata": { + "file_size": 597, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob123_bugs_addsubz_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_460", + "file": "Prob031_dff_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input d,\n output reg q\n);\n", + "metadata": { + "file_size": 62, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob031_dff_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_461", + "file": "Prob023_vector100r_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [99:0] in,\n output reg [99:0] out\n);\n", + "metadata": { + "file_size": 66, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob023_vector100r_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_462", + "file": "Prob067_countslow_prompt.txt", + "task_type": "code_completion", + "content": "\nBuild a decade counter that counts from 0 through 9, inclusive, with a\nperiod of 10. The reset input is active high synchronous, and should\nreset the counter to 0. We want to be able to pause the counter rather\nthan always incrementing every clock cycle, so the \"slowena\" input if\nhigh indicates when the counter should increment.\n\nmodule TopModule (\n input clk,\n input slowena,\n input reset,\n output reg [3:0] q\n);\n\n", + "metadata": { + "file_size": 422, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob067_countslow_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_463", + "file": "Prob127_lemmings1_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input areset,\n input bump_left,\n input bump_right,\n output walk_left,\n output walk_right\n);\n", + "metadata": { + "file_size": 131, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob127_lemmings1_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_464", + "file": "Prob094_gatesv_prompt.txt", + "task_type": "code_completion", + "content": "\nYou are given a four-bit input vector in[3:0]. We want to know some\nrelationships between each bit and its neighbour:\n\n (1) out_both: Each bit of this output vector should indicate whether\n both the corresponding input bit and its neighbour to the left (higher\n index) are '1'. For example, out_both[2] should indicate if in[2] and\n in[3] are both 1. Since in[3] has no neighbour to the left, the answer\n is obvious so we don't need to know out_both[3].\n\n (2) out_any: Each bit of this output vector should indicate whether any\n of the corresponding input bit and its neighbour to the right are '1'.\n For example, out_any[2] should indicate if either in[2] or in[1] are 1.\n Since in[0] has no neighbour to the right, the answer is obvious so we\n don't need to know out_any[0].\n\n (3) out_different: Each bit of this output vector should indicate\n whether the corresponding input bit is different from its neighbour to\n the left. For example, out_different[2] should indicate if in[2] is\n different from in[3]. For this part, treat the vector as wrapping\n around, so in[3]'s neighbour to the left is in[0].\n\nmodule TopModule (\n input [3:0] in,\n output [2:0] out_both,\n output [3:1] out_any,\n output [3:0] out_different\n);\n\n", + "metadata": { + "file_size": 1241, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob094_gatesv_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_465", + "file": "Prob066_edgecapture_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input reset,\n input [31:0] in,\n output reg [31:0] out\n);\n", + "metadata": { + "file_size": 94, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob066_edgecapture_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_466", + "file": "Prob025_reduction_prompt.txt", + "task_type": "code_completion", + "content": "\nParity checking is often used as a simple method of detecting errors when\ntransmitting data through an imperfect channel. Create a circuit that\nwill compute a parity bit for a 8-bit byte (which will add a 9th bit to\nthe byte). We will use \"even\" parity, where the parity bit is just the\nXOR of all 8 data bits.\n\nmodule TopModule (\n input [7:0] in,\n output parity\n);\n\n", + "metadata": { + "file_size": 370, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob025_reduction_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_467", + "file": "Prob060_m2014_q4k_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input resetn,\n input in,\n output out\n);\n", + "metadata": { + "file_size": 77, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob060_m2014_q4k_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_468", + "file": "Prob109_fsm1_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input clk,\n input in,\n input areset,\n output out\n);\n", + "metadata": { + "file_size": 77, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob109_fsm1_ifc.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_469", + "file": "Prob066_edgecapture_prompt.txt", + "task_type": "code_completion", + "content": "\nFor each bit in a 32-bit vector, capture when the input signal changes\nfrom 1 in one clock cycle to 0 the next. \"Capture\" means that the output\nwill remain 1 until the register is reset (active high synchronous\nreset).\n\nmodule TopModule (\n input clk,\n input reset,\n input [31:0] in,\n output reg [31:0] out\n);\n\n", + "metadata": { + "file_size": 315, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob066_edgecapture_prompt.txt" + } + }, + { + "source": "verilog_eval_v2", + "dataset": "dataset_code-complete-iccad2023", + "id": "veval_470", + "file": "Prob113_2012_q1g_ifc.txt", + "task_type": "code_completion", + "content": "\nmodule TopModule (\n input [4:1] x,\n output logic f\n);\n", + "metadata": { + "file_size": 57, + "file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob113_2012_q1g_ifc.txt" + } + } +] \ No newline at end of file