s="rvts32">Added memory read/write conditional breakpoint capability</span></li>
 <li class="rvps5"><span class="rvts32">Added illegal opcode support for breakpoints</span></li>
 <li class="rvps5"><span class="rvts32">Support for 'S' register in conditional debugger breakpoints</span></li>
 <li class="rvps5"><span class="rvts32">Syntax highlight of disassembly</span></li>
 <li class="rvps5"><span class="rvts32">Fixed corruption of PPU reset while debugging</span></li>
 <li class="rvps5"><span class="rv