>
<td class="label">From</td>
<td>corescorecore/core_4/serving/ram/mem_mem_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>corescorecore/core_4/serving/ram/mem_mem_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkgen/u_pll/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkgen/u_pll/CLKOUT.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th