nd data cache with sizes of <span class="XML-Token">[0;4;8;16;32;64]KB</span>. Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors.</p>
<p>All cache maintenance operations are executed by writing to registers in the memory mapped System Control Space (SCS) region of the internal PPB memory space.</p>
<dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before ena