odes the source register.</p>
<p>Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /2, or EVEX.128.66.0F 71-73 /2), VEX.vvvv/EVEX.vvvv encodes the destination register.</p>
<h2 id="operation">Operation<a class="anchor" href="#operation">
			¶
		</a></h2>
<h3 id="psrlw--with-64-bit-operand-">PSRLW (with 64-bit operand)<a class="anchor" href="#psrlw--with-64-bit-operand-">
			¶
		</a></h3>
<pre>IF (COUNT &gt; 15)
THEN
    DEST[64:0] ← 0000000000000000H
ELSE
    DEST[15:0] ← ZeroExtend(DEST[1