d>50.804</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.750</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>62.553</td>
</tr>
<tr>
<td class="label">From</td>
<td>corescorecore/core_23/serving/ram/mem_mem_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>corescorecore/core_23/serving/ram/mem_mem_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkgen/u_pll/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkgen/u_pll/CLKOUT.default_ge