and Cortex-M0+ </th><th>Register Name  </th></tr>
<tr>
<th colspan="4">Nested Vectored Interrupt Controller (NVIC) Register Access  </th></tr>
<tr>
<td>NVIC-&gt;ISER[] </td><td>NVIC_ISER0..7 </td><td>ISER </td><td>Interrupt Set-Enable Registers  </td></tr>
<tr>
<td>NVIC-&gt;ICER[] </td><td>NVIC_ICER0..7 </td><td>ICER </td><td>Interrupt Clear-Enable Registers  </td></tr>
<tr>
<td>NVIC-&gt;ISPR[] </td><td>NVIC_ISPR0..7 </td><td>ISPR </td><td>Interrupt Set-Pending Registers  </td></tr>
<tr>
<td>NVIC-&gt;ICPR[]