    ["vm"],
		Verilog:     ["v|vh|sv|svh"],
		VHDL:        ["vhd|vhdl"],
		Wollok:      ["wlk|wpgm|wtest"],
		XML:         ["xml|rdf|rss|wsdl|xslt|atom|mathml|mml|xul|xbl|xaml"],
		XQuery:      ["xq"],
		YAML:        ["yaml|yml"],
		Django:      ["html"]
	};
	for (var key in supportedModes) {
		if (supportedModes.hasOwnProperty(key)) {
			var thisExtension = supportedModes[key][0].split("|");
			if (thisExtension.length == 1){
				if (ext == thisExtension[0]){
					return key;
				}
			}else{
				for(var i 