/01:35:57.774
   Output C-Matrix:  &lt;second C-matrix&gt;
 
   Input  s/c clock count:  2 / 20550:37
   Output s/c clock count:  2/20550.36.768
   Output UTC:              79-187/07:23:57.774
   Output C-Matrix:  &lt;third C-matrix&gt;
 
   Input  s/c clock count:  2 / 20564:19
   Output s/c clock count:  2/20564.19.768
   Output UTC:              79-187/18:22:21.774
   Output C-Matrix:  &lt;fourth C-matrix&gt;
</PRE>
<BR><BR>
<A NAME="SCLK01"></A>
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