module, iline, shints, lfatal, iloglevel, lecho)</td></tr>
<tr class="memitem:a8df665277598f22f88b16d4a344dd2f8" id="r_a8df665277598f22f88b16d4a344dd2f8"><td class="memItemLeft" align="right" valign="top">subroutine&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8df665277598f22f88b16d4a344dd2f8">assert_1bit</a> (lcondition, smessage, smodule, iline, scalledby, icalledbyline, shints)</td></tr>
<tr class="memitem:a5d1b1c54a37144a0f9be4666cba67cc5" id="r_a5d1b1c54a37144a0f9be4666cba67