scLeft">&#160;</td><td class="mdescRight">Functions for the level-1 data cache. <br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>Functions for level-1 instruction and data cache. </p>
<p>Enhanced Cortex processors (like M7 and M55) include a memory system, which includes an optional Harvard level-1 data and instruction cache with ECC. The optional CPU cache has an instruction a