r>
<tr>
<td>XILINX_EDK</td>
<td>D:\Xilinx\14.7\ISE_DS\EDK</td>
<td>D:\Xilinx\14.7\ISE_DS\EDK</td>
<td>D:\Xilinx\14.7\ISE_DS\EDK</td>
<td>D:\Xilinx\14.7\ISE_DS\EDK</td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
<td>D:\Xilinx\14.7\ISE_DS\PlanAhead</td>
<td>D:\Xilinx\14.7\ISE_DS\PlanAhead</td>
<td>D:\Xilinx\14.7\ISE_DS\PlanAhead</td>
<td>D:\Xilinx\14.7\ISE_DS\PlanAhead</td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
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<TR ALIGN=CENTER BG