itical_priority_level=15</TD>
    <TD>pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32)</TD>
    <TD>pcw_ddr_lpr_to_critical_priority_level=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ddr_peripheral_clksrc=DDR PLL</TD>
    <TD>pcw_ddr_port0_hpr_enable=0</TD>
    <TD>pcw_ddr_port1_hpr_enable=0</TD>
    <TD>pcw_ddr_port2_hpr_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ddr_port3_hpr_enable=0</TD>
    <TD>pcw_ddr_write_to_critical_priority_level=2</TD>
    <TD>pcw_ddrpll_ctrl_fbdiv=32</TD>
    <TD>pcw_en