
<p>VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.L must be 0, other-wise the instruction will #UD.</p>
<h2>Operation</h2>
<p><strong>PINSRW (with 64-bit source operand)</strong></p>
<pre>    SEL ← COUNT AND 3H;
         CASE (Determine word position) OF
              SEL ← 0:
                              MASK ← 000000000000FFFFH;
              SEL ← 1:
                              MASK ← 00000000FFFF0000H;
              SEL ← 2:
                  