 causes for resets.\n NOTE 1: All bits in this register, including reserved bits, are writable. Therefore care should be taken not to write this register.\n NOTE 2:  This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.</p>
                <h3>Example Macro Usage:</h3>
                <pre style="margin:10px" class="language-pascal"><span style='color:#3f7f59; '>//
// Register access is all performed through the standard CMS