D>pcw_enet_reset_polarity=Active Low</TD>
    <TD>pcw_fclk0_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_fclk1_peripheral_clksrc=IO PLL</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_fclk2_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_fclk3_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_fpga0_peripheral_freqmhz=50</TD>
    <TD>pcw_fpga1_peripheral_freqmhz=50</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_fpga2_peripheral_freqmhz=50</TD>
    <TD>pcw_fpga3_peripheral_freqmhz=50</TD>
    <TD>pcw_fpga_fclk0_enable=1</TD>
    <TD