.....

4. RESOLVED ISSUES


  4.1 ISE 
  
      Resolved issue with example design becoming core top in planAhead

      Resolved issue with Virtex6 MMCM instantiation for VHDL project
      Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A>

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5. KNOWN ISSUES & LIMITATIONS


  5.1 ISE 
  
  
  The most recent information, including known issues, work