o set XCR0[2] (AVX state) while clearing XCR0[1] (SSE state); it is necessary to set both bits to use AVX instructions; Section 13.3, “Enabling the XSAVE Feature Set and XSAVE-Supported Features,” of <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1</em>.</p>
<h2>Operation</h2>
<pre>XCR[ECX] ← EDX:EAX;</pre>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>XSETBV:</p>
<p>void _xsetbv( unsigned int, unsigned __int64);</p>
<h2>Protec