hen enabled,
the following additional indenting options can be set:
<ul>

<li><b>Indentation per level:</b> This specifies the number of
characters to indent for each level of scope in the Verilog module.

<li><b>Make begin..end flush with enclosing level:</b> If this feature
is enabled, any "begin..end" blocks will be indented the same amount
as the statement that encloses it (e.g., the parent "if" statement).

<li><b>Auto indent after return:</b> If this feature is enabled,
TkGate will fix formatting each