128.7

// Macro definition
`define BUS_WIDTH = 8;

// Module definition
module block(
  input                   clk,
  input                   rst_n,
  input  [`BUS_WIDTH-1:0] data_in,
  output [`BUS_WIDTH-1:0] data_out
);
  
  always @(posedge clk or negedge rst_n) begin

    if (~rst_n) begin
      data_out <= 8'b0;
    end else begin
      data_out <= data_in;
    end
    
    if (~rst_n)
      data_out <= 8'b0;
    else
      data_out <= data_in;
    
    if (~rst_n)
      begin
        data_out <= 8'b0