stination are set to zero.</p>
<p>128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.</p>
<p>VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.</p>
<h2>Operation</h2>
<p><strong>PHMINPOSUW (128-bit Legacy SSE version)</strong></p>
<pre>INDEX ← 0;
MIN ← SRC[15:0]
IF (SRC[31:16] &lt; MIN)
    THEN INDEX ← 1;  MIN ← 