D>pcw_uiparam_ddr_al=0</TD>
    <TD>pcw_uiparam_ddr_bank_addr_count=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_bl=8</TD>
    <TD>pcw_uiparam_ddr_board_delay0=0.25</TD>
    <TD>pcw_uiparam_ddr_board_delay1=0.25</TD>
    <TD>pcw_uiparam_ddr_board_delay2=0.25</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_board_delay3=0.25</TD>
    <TD>pcw_uiparam_ddr_bus_width=32 Bit</TD>
    <TD>pcw_uiparam_ddr_cl=7</TD>
    <TD>pcw_uiparam_ddr_clock_0_length_mm=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pc