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<h1>Overview<a class="headerlink" href="#overview" title="Permalink to this headline">¶</a></h1>
<p>In modern System-On-Chip (SoC) platforms a low-latency and high-bandwidth path to DRAM is critical to meet CPU, GPU, and NPU workloads and performance requirements.</p>
<p>The DDR Physical Interface (PHY) IP provides an interface