metic or logic
operations, while other unit fills the prefetch queue. This way the prefetch
unit can attempt to read from the instruction stream whenever the bus is free
and there is still enough space in the queue. And the CPU can keep its internal
processing as long as operations are pending and data is available. So one unit
normally doesn’t need to wait for the other one. If the prefetch unit is
delayed because external RAM (or ROM) is not fast enough, this won’t necessary
delay internal exec