TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_s_axi_acp=0</TD>
    <TD>c_use_s_axi_gp0=0</TD>
    <TD>c_use_s_axi_gp1=0</TD>
    <TD>c_use_s_axi_hp0=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_s_axi_hp1=0</TD>
    <TD>c_use_s_axi_hp2=0</TD>
    <TD>c_use_s_axi_hp3=0</TD>
    <TD>core_container=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>use_trace_data_edge_detector=0</TD>
    <TD>x_ipcorerevision=6</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD