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          <td class="memname">u8 XDp_TxSinkConfig::LaneStatusAdjReqs[6]</td>
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<p>This is a raw read of the RX device's status registers. </p>
<p>The first 4 bytes correspond to the lane status associated with clock recovery, channel equalization, symbol lock, and interlane alignment. The remaining 2 bytes represent the pre-emphasis