:"D:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.v"
@I::"D:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v"
@I::"D:\Actelprj\1401\5932_sign_cmp\smartgen\cmp_2\cmp_2.v"
@I::"D:\Actelprj\1401\5932_sign_cmp\hdl\com_2c.v"
@I::"D:\Actelprj\1401\5932_sign_cmp\component\work\XYF\XYF.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module XYF
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\Actelprj\1