lication #03</h1>
	<b>Your mission:</b> Create a behavioral Verilog model for the following circuit:
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		<pre id="code" style="width: 800px; border:2px solid #000; padding: 0.5em;"><span class="noedit">module top(input clk, reset, input [7:0] A, output reg [7:0] Y);
  always @(posedge clock) begin</span><span class="edit" contenteditable="true">
    Y &lt;= A | {4{reset}};
  </span><span class="noedit">end
endmodule<