te_b=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>p_width_addr_read_a=5</TD>
    <TD>p_width_addr_read_b=5</TD>
    <TD>p_width_addr_write_a=5</TD>
    <TD>p_width_addr_write_b=5</TD>
</TR><TR ALIGN='LEFT'>    <TD>p_width_col_write_a=106</TD>
    <TD>p_width_col_write_b=106</TD>
    <TD>read_data_width_a=106</TD>
    <TD>read_data_width_b=106</TD>
</TR><TR ALIGN='LEFT'>    <TD>read_latency_a=2</TD>
    <TD>read_latency_b=0</TD>
    <TD>read_reset_value_a=0</TD>
    <TD>read_reset_value_b=0</TD>
</TR><T