re found, it
will then rename the temporary file to the target save file.  When this
option is disabled, the save will occur directly to the target save
file with no consistency checks.

<li><b>Include cells in save files:</b> If this option is enabled,
Verilog modules for TkGate's primitive cells such as AND gates and OR
gates will be included in the save file.  These cells are not needed
by TkGate, but any external simulation or synthesis tool may need
these cells in order to interpret the TkGate save fil