C1[127:64] &gt;&gt; COUNT_1);
ELSE
DEST[127:64] ← 0;
DEST[VLMAX-1:128] ← 0;</pre>
<p><strong>VPSRLVQ (VEX.256 version)</strong></p>
<pre>COUNT_0 ← SRC2[63 : 0];
    (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 ← SRC2[255 : 192];
IF COUNT_0 &lt; 64 THEN
DEST[63:0] ← ZeroExtend(SRC1[63:0] &gt;&gt; COUNT_0);
ELSE
DEST[63:0] ← 0;
    (* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 &lt; 64THEN
DEST[255:192] ← ZeroExtend(SRC1[255:192] &gt;&gt; COUNT_3);
