BYTE_2_|_A_|_Data_BYTE_N_|_NA_|_STOP_|</code></pre>
<p>First of all, through Handle_I2C_Master_TransmitReceive() routine, Master device generate an I2C start condition with the Slave address and a write bit condition. When address Slave match code is received on I2C1, an ADDR interrupt occurs. I2C1 IRQ Handler routine is then checking Address Match Code and direction Write. This will allow Slave to enter in receiver mode and then acknowledge Master to send the Command code bytes through DMA. When acknowledg