system is synthesized and DFT insertion is performed using Synopsys DFT Compiler and &quot;TSMC 130nm CL013G-FSG Process 1.2V Metro<sup>TM</sup> v1.0&quot; Standard Cell Library. The synthesis and DFT insertion is repeated 3 times (once for each mode of operation) to ensure that there is no violations in any mode. There are 3 scripts that are used in the DFT insertion process:</p>
<ol>
    <li>'constraints.tcl': Same constraints of the logic synthesis process but it additionaly defines the scan clock to be 