DrpWr
                    Improved status return of APIs with DRP Rd and Wr
                    Added N2=8 divider for CPLL for HDMI
1.7   gm   13/09/17 Disabled intelligent clock sel in QPLL0/1 configuration
                    Updated DP CDR config for 8.1 Gbps
                    Updated XVPHY_QPLL0_MAX to 16375000000LL
1.8   gm   05/09/18 Enable IPS only when XVphy_GetRefClkSourcesCount
                      returns more than 1.
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