ready</pre>
<pre style="margin:0; padding:0 "> 135:   };</pre>
<pre style="margin:0; padding:0 "> 136: </pre>
<pre style="margin:0; padding:0 "> 137:   // a_ready depends on the FIFO full condition and grant from SRAM (or SRAM arbiter)</pre>
<pre style="margin:0; padding:0 "> 138:   // assemble response, including read response, write response, and error for unsupported stuff</pre>
<pre style="margin:0; padding:0 "> 139: </pre>
<pre style="margin:0; padding:0 "> 140:   // Output to SRAM:</pre>
<pre style="m