p>VPSRLVD <em>ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Shift bits in doublewords in <em>ymm2</em> right by amount spec-ified in the corresponding element of <em>ymm3/m256</em> while shifting in 0s.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F38.W1 45 /r</p>
<p>VPSRLVQ <em>ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Shift bits in quadwords in <em>ymm2</em> right by amount speci-fied in the corresponding element of <em>ymm3/m256</em> while