I_cache_syn_encrypt.edf C:\Users\morpack\Documents\morpack_fpga\hydra\hydra_1/I_cache_syn.edf

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:02m:43s; CPU Time elapsed 0h:02m:41s; Memory used current: 240MB peak: 295MB)

Writing Verilog Simulation files

Finished Writing Verilog Simulation files (Real Time elapsed 0h:02m:44s; CPU Time elapsed 0h:02m:42s; Memory used current: 231MB peak: 295MB)

<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1370949641>