1, bit 63 of the source operand to MOV to CR3 determines whether the instruction invalidates entries in the TLBs and the paging-structure caches (see Section 4.10.4.1, “Operations that Invalidate TLBs and Paging-Structure Caches,” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>). The instruction does not modify bit 63 of CR3, which is reserved and always 0.</p>
<p>See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25 of the <em>Inte