 Slave to enter in receiver mode and then acknowledge Master to send the Command code bytes through DMA. When acknowledge is received on I2C2, DMA transfer the Command code data from flash memory buffer to I2C2 TXDR register. This will allow Master to transmit a byte to the Slave. Each time a byte is received on I2C1 (Slave), an RXNE interrupt occurs and byte is stored into an internal buffer until a STOP condition. And so each time the Slave acknowledge the byte received, DMA transfer the next data from fl