(it is the ratio between the clock frequency of the UART receiver and the clock frequency of the UART transmitter).</td>
    </tr>
</table>
<h4 id="functional-verification">Functional Verification</h4>
<p>This module is verified through self-checking testbench in Modelsim. The testbench can be run using <code>run.tcl</code> script.</p>
<hr>
<h3 id="bus-synchronizer">Bus Synchronizer</h3>
<p>It acts as a gray encoded bus synchronizer or a single bit synchronizer according to the value of the BUS_WIDTH parame