w:work.smart_unit(verilog) inst counter_jump[6:0]

Finished factoring (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:28s; Memory used current: 235MB peak: 235MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:29s; Memory used current: 209MB peak: 247MB)


Clock Buffers:
  Inserting Clock buffer for port HCLK,


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:38s; CPU Time elapsed 0h:00m:38s; Memory use