ash memory buffer to I2C2 TXDR register until Transfer completed. Master auto-generate a Stop condition when DMA transfer is achieved.</p>
<p>The STOP condition generate a STOP interrupt and initiate the end of reception on Slave side. I2C1 IRQ handler and Handle_I2C_Master_Transmit() routine are then clearing the STOP flag in both side.</p>
<p>LED1 is On if data are well sent and the Command Code sent to slave is print in the Terminal I/O.</p>
<pre><code>2. Request Command code :
    a. Type of command whi