h Slave address and a read bit condition. When address Slave match code is received on I2C1, an ADDR interrupt occurs. I2C1 IRQ Handler routine is then checking Address Match Code and direction Read. This will allow Slave to enter in transmitter mode and then send a byte when TXIS interrupt occurs. When byte is received on I2C2, an RXNE event occurs and DMA transfer data from RXDR register to an internal buffer until end of transfer. Master auto-generate a NACK and STOP condition to inform the Slave that th