    <td>register2</td>
        <td>output</td>
        <td align="center">DATA_WIDTH (default value is 8)</td>
        <td>The third register in the register file, it stores the parity configuration (parity enable and parity type) of the UART.</td>
    </tr>
    <tr>
        <td>register3</td>
        <td>output</td>
        <td align="center">DATA_WIDTH (default value is 8)</td>
        <td>The fourth register in the register file, it stores the value of the oversampling prescale used in the clock divider 