li>
    <li>SO: The output from the scan chain. The width of this port is the number of the scan chains</li>
</ul>
<p><strong>Number of scan chains:</strong>
These results are produced after the logic synthesis indicating that there should exist 3 scan chains in the system if each chain has 100 flip-flops.</p>
<img src="docs/screenshots/DFT/preparation.PNG">
<p>The logic of the scan_clk and scan_reset is manually inserted by using 2x1 muxes for all the clocks and resets in the system. The clock gating cell 