is bypassed by connecting its enable pin with (test_mode | enable) (i.e. the clock gating cell will be always enabled in the test mode). This leads to a violation on this cell because it is not controllable.</p>
<img src="docs/screenshots/DFT/violations.PNG">
<p>There are 3 modes of operation after the DFT logic is inserted:</p>
<ol>
    <li>Functional mode: test_mode = 0, SE = 0</li>
    <li>Test scan mode: test_mode = 1, SE = 1</li>
    <li>Test capture mode: test_mode = 1, SE = 0</li>
</ol>
<p>The whole 