rts-setup-and-hold-can-be-found-at-%22logicsynthesislogicsynthesisoutputreports%22">Timing reports (setup and hold) can be found at &quot;logic_synthesis/logic_synthesis_output/reports&quot;</h4>
<h2 id="post---logic-synthesis-formal-verification">Post - Logic Synthesis Formal Verification</h2>
<p>Formal verification takes the original RTL modules (golden RTL files) and the netlist generated fom the synthesis process and performs functional equivalence checking and reports whether the two systems (RTL and n