for one cycle after the ALU result is evaluated.</p>
<img src="docs/screenshots/system_design/system_controller/UART_receiver_controller_FSM.png">
<p>The waveform after executing an ALU operation is shown in the following figure.</p>
<img src="docs/screenshots/functional_verification/system_controller/ALU_clk_enable.PNG">
<p>Note that if any omitted condition occurs, the current state won't change.</p>
<h5 id="port-description">Port Description</h5>
<table>
    <tr>
        <th align="left">Port</th>
      