NDED). It is used in the Main FSM to transition its state when the transmission has ended.</li>
</ol>
<p>Main FSM: This FSM controls the following output ports according to the current state: transmitter_parallel_data_valid, transmitter_parallel_data, UART_receiver_controller_enable.</p>
<p>The &quot;WAIT_FOR_UPPER_ALU_RESULT&quot; state is used so that the &quot;transmitter_parallel_data_valid&quot; can be set to logic zero during that state, this is done so that the pulse generator can accept a new &quot;