TURE_MTRR	(0*32+12) /* Memory Type Range Registers */<br>
#define X86_FEATURE_PGE		(0*32+13) /* Page Global Enable */<br>
#define X86_FEATURE_MCA		(0*32+14) /* Machine Check Architecture */<br>
#define X86_FEATURE_CMOV	(0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */<br>
#define X86_FEATURE_PAT		(0*32+16) /* Page Attribute Table */<br>
#define X86_FEATURE_PSE36	(0*32+17) /* 36-bit PSEs */<br>
#define X86_FEATURE_PN		(0*32+18) /* Processor serial number */<br>
#define X86_FEATURE_CLFLS