ic Synthesis</h2>
<p>The whole system is synthesized using Synopsys Design Compiler and &quot;TSMC 130nm CL013G-FSG Process
1.2V Metro<sup>TM</sup> v1.0&quot; Standard Cell Library. There are 3 scripts that are used in the synthesis process:</p>
<ol>
    <li>'constraints.tcl': It defines all clock source using 'create_clock' and 'create_generated_clock', defines asynchronous clock groups using 'set_clock_groups -asynchronous', sets input and output delays, sets the output load on the output ports, and sets 