ADC_RDYF and SYSCFG_CFGR3_VREFINT_COMP_RDYF defines.</p></li>
<li>Aligned register namings with the different L0 Reference Manual (For STM32L0x1 : RM0377 Rev5, for STM32L0x2 : RM0367 Rev2, for STM32L0x3 : RM0367 Rev4). The list of the modification is listed hereafter :
<ul>
<li>Introduced new masks in EXTI bit definitions in order to simplify LL source code.</li>
<li>Renamed RCC_CFGR_MCO_x into RCC_CFGR_MCOSEL_x</li>
<li>Added FLASHSIZE_BASE, UID_BASE and SRAM_SIZE_MAX defines.</li>
<li>Renamed macro IS_DMA