s software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@N: : <!@TM:1370949471> | : Running Verilog Compiler in System Verilog mode 
@I::"C:\Synopsys\fpga_G201209SP1\lib\xilinx\unisim_m10i.v"
@I::"C:\Synopsys\fpga_G201209SP1\lib\xilinx\unisim.v"
@I::"C:\Synopsys\fpga_G201209SP1\lib\vlog\umr_capim.v"
@I::"C:\Synopsys\fpga_G201209SP1\lib\vlog\scemi_objects.v"
@I::"C:\Synopsys\fpga_G201209SP1\lib\vlog\scemi_pipes.svh"
@I::"C:\Synop