erification_script.tcl' and produces the log file which contains all the steps of the formal verification and their outputs and cleans the directory from temporary files after the verification is done.</li>
</ol>
<h4 id="verification-results">Verification Results</h4>
<img src="docs/screenshots/formal_verification/post-logic_synthesis.PNG">
<hr>
<h2 id="design-for-testability-dft">Design For Testability (DFT)</h2>
<p>DFT is used to insert additional logic (not for functional mode) to ensure that chip is fre