into the destination operand (first operand). The destination may be either an XMM register or a 128-bit memory location.</p>
<p>VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
<p>The high 7 bits of the immediate are ignored.</p>
<p>An attempt to execute VEXTRACTI128 encoded with VEX.L= 0 will cause an #UD exception.</p>
<h2>Operation</h2>
<p><strong>VEXTRACTI128 (memory destination form)</strong></p>
<pre>CASE (imm8[0]) OF
    0: DEST[127:0] ← SRC1[127:0]
    1: DEST[127:0] �