ructural modelling, and FSM coding) of all the system blocks from scratch (UART transmitter and receiver, integer clock divider, ALU, register file, parametrized data and bit synchronizers, reset synchronizer, and system's main controller).</li>
    <li>Solving CDC issues by using synchronizers.</li>
    <li>Functional verification using self-checking testbenches and automated Python verification environments and running the testbenches using Modelsim.</li>
    <li>Logic synthesis using Synopsys Design Comp