class="keyword">end</span>

<span class="comment">% input and internal capacitance of gates and the driving resistance</span>
Cin_norm  = ones(N,1);
Cint_norm = ones(N,1);
Rdrv_norm = ones(N,1);

<span class="comment">% place extra capacitance before the input of the 5th inverter</span>
Cin_norm(5) = 80;

<span class="comment">% primary output has Cin capacitance (but has no Cload)</span>
Cin_po = sparse(M,1);
Cin_po(primary_outputs) = CL;

<span class="comment">% primary input has Cload capacitance (but ha