e is received on I2C2, DMA transfer the Command code data from flash memory buffer to I2C2 TXDR register. This will allow Master to transmit a byte to the Slave. Each time a byte is received on I2C1 (Slave), an RXNE interrupt occurs and byte is stored into an internal buffer until a RESTART condition. And so each time the Slave acknowledge the byte received, DMA transfer the next data from flash memory buffer to I2C2 TXDR register until Transfer completed. Then Master device generate a RESTART condition wit