ic timing analysis (the corners are defined by the fast-fast library and slow-slow library).</p>
<h3 id="floor-planning">Floor Planning</h3>
<p>The chip size is 240.67x160.0 Î¼m<sup>2</sup>.</p>
<img src="docs/screenshots/physical_design/floor_plan.PNG">
<h3 id="power-planning">Power Planning</h3>
<p>The power planning step is performed to reduce the IR drop and minimize the effect of electromigration. In this step: power rings, power stripes, and power rails are inserted.</p>
<img src="docs/screenshots/p