ts\morpack_fpga\hydra\top_controller_v2.v:561:2:561:8:@N::@XP_MSG">top_controller_v2.v(561)</a><!@TM:1370949641> | Found counter in view:work.Hydra_controller(verilog) inst counter_inst[8:0]
Encoding state machine curstate[9:0] (view:work.Hydra(verilog))
original code -> new code
   0000 -> 0000000001
   0010 -> 0000000010
   0011 -> 0000000100
   0100 -> 0000001000
   0101 -> 0000010000
   0110 -> 0000100000
   0111 -> 0001000000
   1000 -> 0010000000
   1001 -> 0100000000
   1111 -> 1000000000