 the clock divider (oversampling_prescale), it is connected to register_file[3].</td>
    </tr>
    <tr>
        <td>output_clk</td>
        <td>output</td>
        <td align="center">1</td>
        <td>The output divided clock (UART_transmitter_clk).</td>
    </tr>
</table>
<h4 id="functional-verification">Functional Verification</h4>
<p>This module is verified through logic simulation in Modelsim. The simulation can be run using <code>run.tcl</code> script.</p>
<br>
<p>Test case (1) (division_ratio = 3)</