there is any timing violation.</p>
<img src="docs/screenshots/physical_design/route.PNG">
<h3 id="chip-finishing">Chip Finishing</h3>
<p>Insert filler cells, generate gate level netlist (used in gate-level simulation (GLS)), gate level netlist with PG pins (used for analog IR drop simulation), SDF file (used in GLS), and GDS file which is used in manufacturing of the chip.</p>
<img src="docs/screenshots/physical_design/final_chip.PNG">
<h2 id="post---physical-design-formal-verification">Post - Physical Desi