:"D:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\proasic3.v"
@I::"D:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v"
@I::"D:\Actelprj\1128\5932_74HC283\hdl\5932_74HC283.v"
Verilog syntax check successful!
Selecting top level module HC283
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\Actelprj\1128\5932_74HC283\hdl\5932_74HC283.v:2:7:2:12:@N:CG364:@XP_MSG">5932_74HC283.v(2)</a><!@TM:1385701509> | Synthesizing module HC283

@END
Process took 0h:00m:01s realtime, 0h: