iler &amp; 130 nm technology node.</li>
    <li>Formal verification post logic synthesis using Synopsys Formality.</li>
    <li>Design for testability (DFT) using Synopsys DFT Compiler.</li>
    <li>Formal verification post DFT using Synopsys Formality.</li>
    <li>Physical design (floor planning, power planning, placement, CTS, routing, timing closure, and chip finishing) using Cadence innovus.</li>
    <li>Formal verification post physical design using Synopsys Formality.</li>
</ol>
<h2 id="table-of-cont