al file.</li>
    <li>Generates all the expected results that should be transmitted serially through the UART transmitter in an external file.</li>
    <li>Generates the memory file which corresponds to the final values that should be stored in the register file after the execution of all the commands.</li>
    <li>Compares the results of the Verilog testbench (transmitted through UART transmitter) and the generated memory file with the expected results' file and expected memory file.</li>
    <li>Reports a