0;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga8a2d599082b9fe56cee1c6454bb3c6a1">ARM_NAND_BUS_DDR2_CMPR</a>&#160;&#160;&#160;(1UL &lt;&lt; 18)</td></tr>
<tr class="memdesc:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Enable complementary RE_n (RE_c) signal.  <a href="group__nand__bus__mode__codes.html#ga8a2d599082b9fe56cee1c6454bb3c6a1"></a><br/></td></tr>
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