TURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */<br>
#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */<br>
#define X86_FEATURE_PEBS	(3*32+12)  /* Precise-Event Based Sampling */<br>
#define X86_FEATURE_BTS		(3*32+13)  /* Branch Trace Store */<br>
/* 14 free */<br>
#define X86_FEATURE_SYNC_RDTSC	(3*32+15)  /* RDTSC synchronizes the CPU */<br>
#define X86_FEATURE_REP_GOOD   (3*32+16) /* rep microcode works well on this CPU */<br>
<br>
/* Intel-defined CPU features, CPUID le