s="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga10a1ef3be69bfa7e6cc657bee751a077">ARM_NAND_BUS_DDR2_DO_WCYC_2</a>&#160;&#160;&#160;(0x02UL &lt;&lt; ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
<tr class="memdesc:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Output Warmup cycles: 2.  <a href="group__nand__bus__mode__codes.html#ga10a1ef3be69bfa7e6cc