t</td>
        <td align="center">2 * DATA_WIDTH (default value is 16)</td>
        <td>The result of the ALU.</td>
    </tr>
</table>
<h4 id="functional-verification">Functional Verification</h4>
<p>This module is verified through self-checking testbench in Modelsim. The testbench can be run using <code>run.tcl</code> script.</p>
<hr>
<h3 id="register-file">Register File</h3>
<h4 id="port-decription">Port Decription</h4>
<table>
    <tr>
        <th align="left">Port</th>
        <th>Direction</th>
       