t triggering mode, type, secure access and target CPUs of the interrupt (see <a class="el" href="group__irq__mode__defs.html">IRQ Mode Bit-Masks</a>) identified by the irqn parameter.</p>
<p>For Arm GIC the default implementation looks like the following example:</p>
<div class="fragment"><div class="line">int32_t <a class="code" href="group__irq__ctrl__gr.html#gab35da69354d2e515931580a1308a3a85">IRQ_SetMode</a> (<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a> irqn, 