� SRC1[255:128]
ESAC.</pre>
<p><strong>VEXTRACTI128 (register destination form)</strong></p>
<pre>CASE (imm8[0]) OF
    0: DEST[127:0] ← SRC1[127:0]
    1: DEST[127:0] ← SRC1[255:128]
ESAC.
DEST[VLMAX-1:128] ← 0</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VEXTRACTI128:</p>
<p> __m128i _mm256_extracti128_si256(__m256i a, int offset);</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None</p>
<h2>Other Exceptions</h2>
<p>See Exceptions Type 6; additionally</p>
<table class="exception-table"