*</pre>
<pre style="margin:0; padding:0 ">   6:  * Tile-Link UL adapter for SRAM-like devices</pre>
<pre style="margin:0; padding:0 ">   7:  *</pre>
<pre style="margin:0; padding:0 ">   8:  * - Intentionally omitted BaseAddr in case of multiple memory maps are used in a SoC,</pre>
<pre style="margin:0; padding:0 ">   9:  *   it means that aliasing can happen if target slave size in TL-UL crossbar is bigger</pre>
<pre style="margin:0; padding:0 ">  10:  *   than SRAM size</pre>
<pre style="margin:0; padding: