the MDIO clock must be setup. This driver will set a safe default that should work with PLB bus speeds of up to 150 MHz and keep the MDIO clock below 2.5 MHz. If the user wishes faster access to the PHY then the clock divisor can be set to a different value (see <a class="el" href="xlltemac_8c.html#a13">XLlTemac_PhySetMdioDivisor()</a>).<p>
MII register access is performed through the functions XLlTemac_PhyRead() and XLlTemac_PhyWrite().<p>
<h2>Link Sync</h2>
<p>
When the device is used in a multispeed envi