chance to be</pre>
<pre style="margin:0; padding:0 "> 243:   //    back pressured, the response FIFO should store the returned data not to</pre>
<pre style="margin:0; padding:0 "> 244:   //    lose the data from the SRAM interface. Remember, SRAM interface doesn't</pre>
<pre style="margin:0; padding:0 "> 245:   //    have back-pressure signal such as read_ready.</pre>
<pre style="background-color: #C0C0C0; margin:0; padding:0 "> 246:   prim_fifo_sync #(</pre>
<pre style="background-color: #C0C0C0; margin:0;