}}-->&nbsp;<!--kadov_tag{{</spaces>}}-->The 
 options are Low, High and FPGA.</span></b></p></li>
	
	<li class=kadov-p-Cwhs8><p class=whs8
								style="font-family: arial, sans-serif;
										font-size: 10pt;
										font-weight: bold;"><b><span style="font-weight: bold;"><B>Collapsing 
 P-Term Limit -- </B></span></b><span style="font-weight: normal;">This option 
 controls the degree to which the fitter flattens a design netlist. A logic 
 gate can collapse forward into a subsequent gate only if the