hysical_design/power_plan.PNG">
<h3 id="placement">Placement</h3>
<p>Place the stanard cells and optimize if there is any timing violation.</p>
<img src="docs/screenshots/physical_design/place.PNG">
<h3 id="clock-tree-synthesis-cts">Clock Tree Synthesis (CTS)</h3>
<p>Build the clock tree to minimize the clock skew between registers and optimize if there is any timing violation.</p>
<img src="docs/screenshots/physical_design/CTS.PNG">
<h3 id="routing">Routing</h3>
<p>Route the standard cells and optimize if 