@I::"C:\Users\morpack\Documents\morpack_fpga\hydra\hydra_wrapper_v2.v"
@I::"C:\Users\morpack\Documents\morpack_fpga\hydra\MasterSlave_TRI.v"
Verilog syntax check successful!
# Tue Jun 11 19:17:50 2013

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@N: : <!@TM:1370949471> | : Running Verilog Compiler in System Verilog mode 
@I::"C:\Synopsys\fpga_G201209SP1\lib\xilinx\unisim_m10i.v"
@I::"C:\Synopsys\fpga_G201209SP1\lib\xilinx\unisim.v"
@I::"C:\Synopsys\fpga_G201209SP1\lib\vlog\umr_capi