UL &lt;&lt; 17)</td></tr>
<tr class="memdesc:gad38354e4a34adbf881afc7f89ff06e89"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Enable complementary DQS (DQS_c) signal.  <a href="group__nand__bus__mode__codes.html#gad38354e4a34adbf881afc7f89ff06e89"></a><br/></td></tr>
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<tr class="memitem:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="memItemLeft" align="right" valign="top">#define&#16