ta Required Time</td>
<td>62.553</td>
</tr>
<tr>
<td class="label">From</td>
<td>corescorecore/core_22/serving/cpu/bufreg/data_31_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>corescorecore/axis_mux/arb_inst/mask_reg_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clkgen/u_pll/CLKOUT.default_gen_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clkgen/u_pll/CLKOUT.default_gen_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY