" href="group__nand__bus__mode__codes.html#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5">ARM_NAND_BUS_DDR2_DI_WCYC_4</a>&#160;&#160;&#160;(0x03UL &lt;&lt; ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
<tr class="memdesc:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warmup cycles: 4.  <a href="group__nand__bus__mode__codes.html#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"></a><br/></td></tr>
<tr class="separator:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="memSeparator