er">1</td>
        <td> A signal to indicate that the start bit or the stop bit was incorrect.</td>
    </tr>
</table>
<h4 id="uart-receiver-finite-state-machine-fsm">UART Receiver Finite State Machine (FSM)</h4>
<img src="docs/screenshots/system_design/UART/UART_receiver/UART_receiver_FSM.png">
<p>Note that if any omitted condition occurs, the current state won't change.</p>
<table>
    <tr>
        <th align="left">Port</th>
        <th>Direction</th>
        <th>Width</th>
        <th>Description</th>
  