160;&#160;<a class="el" href="group__pdm__4l.html#gga2fd171a58c0d33ff28ef0ba181f60c0daa4ac0110ad77bf9e8a2c6473058dfe2e">AM_HAL_PDM_CLKOUT_PHSDLY_CYCLE1</a> = 1
, <br />
&#160;&#160;<a class="el" href="group__pdm__4l.html#gga2fd171a58c0d33ff28ef0ba181f60c0da6f458a756582e72175d4d08f06ae26bd">AM_HAL_PDM_CLKOUT_PHSDLY_NONE</a> = 0
<br />
 }</td></tr>
<tr class="memdesc:ga2fd171a58c0d33ff28ef0ba181f60c0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDMA_CKO clock phase delay in terms of PDMCLK period