yn_sample_clock_path==CKID0001@|M:ClockId0001 @XP_NAMES_BY_PROP">ClockId0001</a>       HCLK                port                   1903       uMasterSlave.ext_inst_input_addr_counter[29]
====================================================================================================================
===== Gated/Generated Clocks =====
************** None **************
----------------------------------
==================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing A