\hydra\MasterSlave_TRI.v:26:7:26:22:@N:CG364:@XP_MSG">MasterSlave_TRI.v(26)</a><!@TM:1370949471> | Synthesizing module MasterSlave_TRI

<font color=#A52A2A>@W:<a href="@W:CS263:@XP_HELP">CS263</a> : <a href="C:\Users\morpack\Documents\morpack_fpga\hydra\MasterSlave_TRI.v:170:21:170:29:@W:CS263:@XP_MSG">MasterSlave_TRI.v(170)</a><!@TM:1370949471> | Port-width mismatch for port S_HBURST. Formal has width 3, Actual 1</font>
<font color=#A52A2A>@W:<a href="@W:CS263:@XP_HELP">CS263</a> : <a href="C:\Users\mor