span class="comment">% gate delay is the product of its driving resistance and load cap.</span>
    Cload = cvx( zeros(N,1) );
    <span class="keyword">for</span> gate = 1:N
      <span class="keyword">if</span> ~ismember( FO{gate}, primary_outputs )
        Cload(gate) = sum( Cin(FO{gate}) );
      <span class="keyword">else</span>
        Cload(gate) = Cin_po( FO{gate} );
      <span class="keyword">end</span>
    <span class="keyword">end</span>

    <span class="comment">% delay</span>
    D = 0.69*one