eiver mode and then acknowledge Master to send the bytes. When acknowledge is received on I2C2, a TXIS event occurs. This will allow Master to transmit a byte to the Slave. Each time a byte is received on I2C1 (Slave), an RXNE interrupt occurs until a STOP condition. And so each time the Slave acknowledge the byte received a TXIS event occurs on Master side. Master auto-generate a Stop condition when size of data to transmit is achieved.</p>
<p>The STOP condition generate a STOP interrupt and initiate the e