ign="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga42560a1f046e20cc4956276156c4ce25">ARM_NAND_BUS_DDR2_DI_WCYC_1</a>&#160;&#160;&#160;(0x01UL &lt;&lt; ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
<tr class="memdesc:ga42560a1f046e20cc4956276156c4ce25"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warmup cycles: 1.  <a href="group__nand__bus__mode__codes.html#ga42560a1f046e20cc4956276156c4ce25"></a>