rithmetic operations, logical operations, register file read &amp; write operations) which are received from an external source through <strong>UART</strong> receiver module and it transmits the commands' results through the <strong>UART</strong> transmitter module.</p>
<p>This is a full ASIC design project (from RTL to GDS). It goes through the ASIC design flow from frontend to backend:</p>
<ol>
    <li>System's architecture design.</li>
    <li>Synthesizable Verilog RTL modelling (behavioral modelling, st