ter. It consists of multiple registers (single bit or multiple bits) connected in a cascaded scheme, and the number of stages is parametrized with a default value of 2.</p>
<h4 id="logic-diagram">Logic Diagram</h4>
<img src="docs/screenshots/system_design/bus_synchronizer/bus_synchronizer.png">
<h4 id="port-description">Port Description</h4>
<table>
    <tr>
        <th align="left">Port</th>
        <th>Direction</th>
        <th>Width</th>
        <th>Description</th>
    </tr>
    <tr>
        <td>clk</t