 ← ZeroExtend(SRC1[31:0] &gt;&gt; COUNT_0);
ELSE
DEST[31:0] ← 0;
    (* Repeat shift operation for 2nd through 7th dwords *)
IF COUNT_7 &lt; 32 THEN
DEST[255:224] ← ZeroExtend(SRC1[255:224] &gt;&gt; COUNT_7);
ELSE
DEST[255:224] ← 0;</pre>
<p><strong>VPSRLVQ (VEX.128 version)</strong></p>
<pre>COUNT_0 ← SRC2[63 : 0];
COUNT_1 ← SRC2[127 : 64];
IF COUNT_0 &lt; 64 THEN
DEST[63:0] ← ZeroExtend(SRC1[63:0] &gt;&gt; COUNT_0);
ELSE
DEST[63:0] ← 0;
IF COUNT_1 &lt; 64THEN
DEST[127:64] ← ZeroExtend(SR