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<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\users\morpack\documents\morpack_fpga\hydra\tbctrl.v:58:0:58:6:@W:MT529:@XP_MSG">tbctrl.v(58)</a><!@TM:1370949473> | Found inferred clock MasterSlave_TRI|HCLK which controls 1827 sequential elements including TriBusControlLogic.MasterDataPhaseSel. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>

syn_allowed_resour