(on an 11th gen Intel laptop). 
            Thus a circuit with 1000 components would run at 50,000 clocks per second. Issie creates fully synchronous circuits 
            with a single clock: logic with asynchronous loops is currently not supported (a feature, since 95% of the time asynchronous circuits cause trouble) 
            although this is on the roadmap for possible implementation in 2023-4. </li>
        <li> Issie designs can be exported to Verilog and synthesised on FPGAs with a simple workflo