base</b>" instantiated <b>altera_avalon_sysid_qsys</b> "<b>sysid</b>"
2011.08.26.15:36:18 [Debug] nios_base: queue size: 58 starting:avalon_read_master "submodules/latency_aware_read_master"
2011.08.26.15:34:27 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files
2011.08.26.15:34:27 [Debug] Command: /home/hwang/altera/11.0/quartus/bin/quartus_map not_a_project --generate_hdl_interface=/home/hwang/sonic/projects/sonic_fpga/src/top_examples/misc/avalon_mm_master/latency_aware_read_master.v --sourc