w. </li>
        <li> User-friendly design entry using a restricted subset of Verilog is supported as an alternative to implementing combinational logic using gates. It is a 
            lot of work implementing a full verilog compiler with Issie's user-frindly error messages, currently the Verilog support is incomplete. We have
            better Verilog support on the roadmap.</li>
        <li>The application comprises about 42K lines of F#, a functional programming language taught by the EEE department 
