fied above will be NACK'ed.</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>For a 5.4Gbps link rate, a high performance 7 series FPGA is required with a speed grade of -2 or -3.</dd></dl>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
</p>
<hr/>
<p>
1.0   als  01/20/15 Initial release. TX code merged from the dptx driver.
2.0   als  06/08/15 Added MST functionality to RX. New APIs:
                        XDp_RxHandleDownReq, XDp_RxGetIicMapEntry,
                        XDp_RxSetIic