 unpredictable behavior across different processor generations.</p>
<h3 id="operation">Operation<a class="anchor" href="#operation">
			¶
		</a></h3>
<h4 id="vsubss--evex-encoded-version-">VSUBSS (EVEX encoded version)<a class="anchor" href="#vsubss--evex-encoded-version-">
			¶
		</a></h4>
<pre>IF (SRC2 *is register*) AND (EVEX.b = 1)
    THEN
        SET_RM(EVEX.RC);
    ELSE
        SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN DEST[31:0]←SRC1[31:0] - SRC2[31:0]
    ELSE
        IF *mergi