e=/home/hwang/sonic/projects/sonic_fpga/src/top_examples/misc/avalon_mm_master/latency_aware_read_master.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt5212_1573600266993779043.dir/0006_sopcqmap/
2011.08.26.15:34:28 [Debug] Command took 1.547s
2011.08.26.15:36:18 [Info] avalon_read_master: "<b>nios_base</b>" instantiated <b>avalon_read_master</b> "<b>avalon_read_master</b>"
2011.08.26.15:36:18 [Debug] nios_base: queue size: 57 starting:avalon_write_master "submodules/write_master"
2011.08.26.15:34:28 [Debug] set