         </td>
                        </tr>

                        <tr>
                            <td>1</td>
                            <td>INTEN</td>
                            <td>RW</td>
                            <td>This bitfield enables the WDT interrupt. Note : This bit must be set before the interrupt status bit will reflect a watchdog timer expiration. The IER interrupt register must also be enabled for a WDT interrupt to be sent to the NVIC.<br><br>
                                </td>
  