 of these instructions additionally to OBI interfaces assertions and to some pipeline assertions.<br>
       After that assertions generation step, the same tool was used to formally verify all those assertions on 2 configurations: CFG_P and CFG_P_F0.</p>
    <p>Then Simulation verification was used to verify what can't be modelized and verified using Formal, like Hardware Loops, Prefetch and Fetch pipeline stages...</p>
    <ul>
        <li>RISC-V ISA Formal Verification Plan:<br>
            The formal ve