ination YMM register are zeroed. VEX.L must be 0, otherwise the instruction will #UD.</p>
<p>VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The first source and destination operands are YMM registers.</p>
<h2>Operation</h2>
<p><strong>PMULHRSW (with 64-bit operands)</strong></p>
<pre>    temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) &gt;&gt;14) + 1;
    temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) &gt;&gt;14) + 1;
    temp2[31:0] = INT32 ((DEST[47: