plain how to correct the error, 
and visual clues. A design aim is to make Issie scalable. 
It is intuitive to use with small 
single-sheet circuits and also highly productive debugging complex CPU designs made from 50 sheets and hundreds of thousands of components.
The motivation for Issie was the observation that during digital lab work in EEE, previously, more time was spent learning to use (or cope with subtle bugs in) 
large commercial hardware design tools, 
than was spent learning digital design. We 