n</h2>
<pre>DEST ← (NOT SRC1) bitwiseAND SRC2;
SF ← DEST[OperandSize -1];
ZF ← (DEST = 0);</pre>
<h2>Flags Affected</h2>
<p>SF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.</p>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>Auto-generated from high-level language.</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None</p>
<h2>Other Exceptions</h2>
<p>See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additio