ly 16-bit signed words, scale and round signed doublewords, pack high 16 bits to <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F38.WIG 0B /r</p>
<p>VPMULHRSW <em>ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to <em>ymm1</em>.</td></tr></table>
<p>NOTES:</p>
<p>1. See note in Section 2.4, “Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software 