rification plan could be found <a href="https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx">here</a>.<br>
        </li>
        <li>Simulation Verification Plans:<br>
            Overall description of simulation verification plans can be found <a href="https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/README.md">here</a>.<br>
            ci_check are run and all v1 legac