on Strategy</a></p>
    <p>For CV32E40Pv2, <b>RISC-V ISA Formal Verification</b> methodology was used and is described <a href="https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_RISCV_vPlan_v1.1.pdf">here</a>.</p>
    <p>Documentation for the various CORE-V cores are maintained in <a href="https://github.com/openhwgroup/programs">programs</a>, the OpenHW Group's CORE-V documentation repo.</p>
    <p></p>
    <p>As much as is practical, we 