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Convert SR F/F to D F/F.
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SR flip-flop to D flip-flop:

Qn Qn+1 R S
0 0 x 0
0 1 0 1
1 0 1 0
1 1 0 x

Excitation table for SR flip flop

Qn Qn+1 D
0 0 0
0 1 0
1 0 1
1 1 0

Excitation table for D flip flop

• In the D flip flop excitation table, when D=0 and Q=0, the next state Q (t+1) is 0. For the next state to remain 0, the value of R and S should be X and 0 respectively. Here, X denotes don’t care value. The value of R in this condition, will not affect the state of the system. R=X and S=0.
• When D=0 and Q=1, the value of Next state Q (t+1) should be 0. (Refer to D flip-flop truth table). Here, there is a transition from 0 to 1 [Q=1 and Q (t+1) =0]. The RS input which corresponds to this transition is S=0 and R=1.
• When D=1 and Q=0, the value of next state Q (t+1) should be 1 (from D flip-flop truth table). Here, there is 0 to 1 transition. The value of R and S should be 0 and 1 respectively. R=0 and S=1.
• When D=1 and Q=1, the value of next state should be equal to 1 (from D flip-flop truth table). Here, there is a transition. The value of R and S corresponding to this transition is 0 and X respectively. X here represents don’t care condition. R=0 and S=X.

K-map simplification:

Logic diagram:

T flip-flop to D flip-flop:

• Both T flip-flop and D flip-flop have only 1 input each, T and D.
• T in the T-Flip flop stands for Toggle flip-flop, which means when the input is high, the output changes or ‘toggles’ its state.
• Thus the truth table and excitation table of T flip-flop are as shown:
T Qn+1
0 Qn
1 Qn

Truth table of a T Flip-Flop

Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0

Excitation table of a T Flip-Flop

• D in the D-Flip flop stands for ‘Delay’ flip-flop, which means the output follows the input after a delay of one clock pulse. Output sets when input is high, and resets when input is low.
• Thus, its truth table and excitation table can be made as:
D Qn+1
0 0 (Reset)
1 (Set)

Truth table of a D Flip-Flop

| Q | | | --- | --- |
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