28/10/2007DSD,USIT,GGSIPU14 VHDL code for shift register entity shiftRegester is Port ( reset,clk,w : in std_logic; q : out std_logic_vector(3 downto 0)); end shiftRegester; architecture Behavioral of shiftRegester is signal temp : std_logic_vector(3 downto 0); begin process(clk,reset) beginif (reset = 0 ) then q 0 ); elsif (clk event and clk= 1 ) then genbits: for i in 3 downto 1 loop temp(i) <= temp(i-1); end loop; temp(0) <= w; end if; q <= temp; end process; end Behavioral;