<reponame>luosichengx/myplace
{"title": "Translation-Triggered Prefetching.", "fields": ["interleaved memory", "memory rank", "universal memory", "memory map", "memory controller"], "abstract": "We propose translation-enabled memory prefetching optimizations or TEMPO, a low-overhead hardware mechanism to boost memory performance by exploiting the operating system's (OS) virtual memory subsystem. We are the first to make the following observations: (1) a substantial fraction (20-40%) of DRAM references in modern big- data workloads are devoted to accessing page tables; and (2) when memory references require page table lookups in DRAM, the vast majority of them (98%+) also look up DRAM for the subsequent data access. TEMPO exploits these observations to enable DRAM row-buffer and on-chip cache prefetching of the data that page tables point to. TEMPO requires trivial changes to the memory controller (under 3% additional area), no OS or application changes, and improves performance by 10-30% and energy by 1-14%.", "citation": "Citations (7)", "year": "2017", "departments": ["Rutgers University"], "conf": "asplos", "authors": ["<NAME>.....http://dblp.org/pers/hd/b/Bhattacharjee:Abhishek"], "pages": 14}