text: Advances in CMOS-compatible photonic elements have made it plausible to exploit nanophotonic communications to overcome the limitations of traditional NoCs. Amongst various proposed nanophotonic architectures, optical crossbars have been shown to provide high performance in terms of bandwidth and latency. In general, optical crossbars provide a vast volume of network resources that are shared among all the cores within the chip. In this paper, we present a fair and efficient admission control mechanism for shared wavelengths and buffer space in optical crossbars. We model buffer management and wavelength assignment as a utility-based convex optimization problem, whose solution determines the admission control policy. Thanks to efficient convex optimization techniques, we obtain the globally optimal solution of the admission control optimization problem by using simple and yet efficient iterative algorithms. We cast our solution procedure as an iterative algorithm to be implemented a central admission controller. Our experimental results corroborate the gain that can be obtained by using such an admission controller to manage the shared resources of the system. Furthermore, they confirm that the proposed admission control algorithm works well for various traffic patterns and parameters, and evinces a tractable scalability with increase in the number of cores of the crossbar.
  @cite_4: SUMMARY Nanophotonics promises to solve the scalability problems of current electrical interconnects thanks to its low sensitivity to distance in terms of latency and energy consumption. Before this technology reaches maturity, hybrid photonic-electronic networks will be a viable alternative. Ideally, ordinary electrical meshes and ring-based photonic networks should cooperate to minimize overall latency and energy consumption, but currently, we lack mechanisms to do this efficiently. In this paper, we present novel fine-grain policies to manage the photonic resources in a tiled chip multiprocessor (CMP) scenario. Our policies are dynamic and base their decisions on parameters such as message size, ring availability, and distance between endpoints, at the message level. The resulting network behavior is also fairer to all cores, reducing processor idle time thanks to faster thread synchronization. All these policies improve performance when compared to the same CMP without the photonic ring, and the most elaborate ones reduce the overall network latency by 50 , execution time by 36 , and network energy consumption by 52 on average, in a 16-core CMP for the PARSEC benchmark suite. Larger hybrid networks with 64 endpoints for 256-core CMPs, based on Corona and Firefly designs, also show far superior throughput and lower latency if managed by one of the proposed policies. Copyright © 2014 John Wiley & Sons, Ltd.
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  @cite_9: The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intra-chip and off-chip communication on the overall power budget. A photonic interconnection network can deliver higher bandwidth and lower latencies with significantly lower power dissipation. We explain why on-chip photonic communication has recently become a feasible opportunity and explore the challenges that need to be addressed to realize its implementation. We introduce a novel hybrid micro-architecture for NoCs combining a broadband photonic circuit-switched network with an electronic overlay packet-switched control network. We address the critical design issues including: topology, routing algorithms, deadlock avoidance, and path-setup tear-down procedures. We present experimental results obtained with POINTS, an event-driven simulator specifically developed to analyze the proposed idea, as well as a comparative power analysis of a photonic versus an electronic NoC. Overall, these results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs.
  @cite_43: To meet energy-efficient performance demands, the computing industry has moved to parallel computer architectures, such as chip multiprocessors (CMPs), internally interconnected via networks-on-chip (NoC) to meet growing communication needs. Achieving scaling performance as core counts increase to the hundreds in future CMPs, however, will require high performance, yet energy-efficient interconnects. Silicon nanophotonics is a promising replacement for electronic on-chip interconnect due to its high bandwidth and low latency, however, prior techniques have required high static power for the laser and ring thermal tuning. We propose a novel nano-photonic NoC (PNoC) architecture, LumiNOC, optimized for high performance and power-efficiency. This paper makes three primary contributions: a novel, nanophotonic architecture which partitions the network into subnets for better efficiency; a purely photonic, in-band, distributed arbitration scheme; and a channel sharing arrangement utilizing the same waveguides and wavelengths for arbitration as data transmission. In a 64-node NoC under synthetic traffic, LumiNOC enjoys 50 lower latency at low loads and @math higher throughput per Watt on synthetic traffic, versus other reported PNoCs. LumiNOC reduces latencies @math versus an electrical 2-D mesh NoCs on the PARSEC shared-memory, multithreaded benchmark suite.
  @cite_13: In conventional hybrid PNoC systems, the end-to end optical data transfer is accompanied with electrical control functions including path-setup, acknowledgment, and tear-down. These functions directly a ect the performance and power characteristics of these circuit-switching based systems. In this paper, we propose a novel hybrid PNoC system, named PHENIC-II. 1 Thanks to the adopted non-blocking photonic switch and light-weight electronic router, PHENIC-II is capable of alleviating the congestion in the electronic control layer which is considered as the main source of latency and power overhead in hybrid PNoC systems. From the performance evaluation, we demonstrate that the proposed system has a better performance and low energy dissipation when compared to the previously proposed systems.
summary: Various approaches have been proposed to exploit nanophotonics for on-chip communication networks. Development of efficient optical data buffers is still a challenging problem, which makes it quite hard to construct a fully optical packet-switched network. As a result, @cite_9 propose a hybrid approach, in which large data packets are transferred using an optical circuit-switched network whereas the optical network is controlled by an electronic packet-switched network. @cite_43 consider the architecture proposed in @cite_9 and propose a predictive switching and reservation technique to reduce its path setup latency. In some other hybrid architectures such as @cite_10 , local communications are carried out by an electrical network, whereas long distance communications utilize optical links. @cite_13 exploit non-blocking photonic switches as well as light-weight electronic routers to decrease the latency and power overheads of hybrid architectures. Garc ' i a- @cite_4 propose a set of policies to manage hybrid networks consisting of ring-based photonic and electrical mesh sub-networks. The proposed policies use different criteria, such as message size, distance, and photonic ring availability, to decide which sub-network to be used for each message.