text: Accelerating inexact string matching procedures is of utmost importance when dealing with practical applications, where huge amount of data must be processed in real time, as usual in bioinformatics or cybersecurity. Inexact matching procedures can yield multiple shadow hits, which must be filtered according to some criterion, to obtain a concise and meaningful list of occurrences. The filtering procedures are often computationally demanding and are performed offline in a post-processing phase. This paper introduces a novel algorithm for Online Approximate String Matching (OASM) able to filter shadow hits on the fly, according to general purpose heuristic rules that greedily assign priorities to overlapping hits. An FPGA hardware implementation of OASM is proposed and compared with a serial software version, showing that even on entry level FPGAs the procedure can reach a high degree of parallelism, with a low usage of logic elements. This makes the proposed architecture very competitive in terms of both performances and cost of the overall computing system.
  @cite_67: In this paper, an efficient FPGA-based hardware algorithm and its extensions are proposed for calculating the edit distance as a degree of similarity between two strings. The proposed algorithms are implemented on FPGA and compared to software programs. Experimental results show the effectiveness of the proposed algorithms.
  @cite_78: 
  @cite_36: 
  @cite_28: This paper presents efficient dataflow schemes for parallel string matching. Two subproblems known as the exact matching and the k-mismatches problems are covered. Three parallel algorithms based on multiple input (and output) streams are presented. Time complexities of these parallel algorithms are O((n d)+ spl alpha ), O spl les spl alpha spl les m, where n and m represent lengths of reference and pattern strings (n spl Gt m) and d represents the number of streams used (the degree of parallelism). We can control the degree of parallelism by using variable number (d) of input (and output) streams. These performances are better than those found in the literature. These algorithms present three different methods to design special purpose systolic array hardware for string matching. With linear systolic array architecture, m PEs are needed for serial design and d*m PEs are needed for parallel design.
  @cite_58: 
  @cite_32: A novel field programmable gate array (FPGA) implementation of content-based music retrieval system is presented in this paper. The system adopts a novel hardware architecture for approximate string matching. The architecture is based on a simple shift-and-or algorithm. It has the advantages of low area cost and high throughput. Numerical results show that the proposed architecture has significantly lower CPU time over its software counterpart running on Pentium IV for large database and or edit distances.
  @cite_44: Text search is a procedure to find occurrences of a pattern in a given text where the pattern and each occurrence may have a limited number of differences. Text search is an indispensable technique for bibliographic databases. In this paper, a restricted class of regular expressions is used as patterns, and all substrings in a text that are close to a pattern, possibly with some errors, are located. We call this text search problem approximate regular expression matching. For this problem, a one-dimensional systolic algorithm is presented based on dynamic programming. Experiments show that the proposed hardware engine implemented on FPGA realizes high-speed text search.
  @cite_79: 
  @cite_40: This paper proposes a high-speed string matching circuit for searching a pattern in a given text. In the circuit, a pattern is specified by a class of restricted regular expressions. The architecture of the proposed circuit is a one-dimensional systolic architecture consisting of simple processing units. It can be effectively used for network intrusion detection systems (NIDSs).
  @cite_80: 
  @cite_47: 
  @cite_68: Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array processor architecture for a wide variety of approximate string matching algorithms to gain high performance at low cost. Further, we describe the architecture of the array and the architecture of the cell in detail in order to efficiently implement for both the preprocessing and searching phases of most string matching algorithms. Further, the architecture performs approximate string matching for complex patterns that contain don't care, complement and classes symbols. We also simulate and evaluate the proposed architecture on a field programmable gate array (FPGA) device using the JHDL tool for synthesis and the Xilinx Foundation tools for mapping, placement, and routing. Finally, our programmable implementation achieves about 8-340 times faster execution than a desktop computer with a Pentium 4 3.5GHz for all algorithms when the length of the pattern is 1024.
  @cite_66: 
summary: FPGA implementations of systolic architectures have been proposed for ASM @cite_67 @cite_36 and, in bioinformatics, for DNA sequence alignment @cite_66 @cite_47 @cite_78 . In the field of Music Information Retrieval (MIR), circuits implementing ASM with dynamic programming cannot retrieve fragments with different sizes @cite_68 and other architectures with higher flexibility only support symbol substitution @cite_28 . Better performance was achieved by Application-Specific Integrated Circuit and FPGA with a comparable computational time on different MIR approaches @cite_32 @cite_79 @cite_58 @cite_80 . An efficient FPGA implementation of ASM has been proposed for text mining, where a restricted class of regular expressions is used to define the patterns to search @cite_44 . A work closely related to this paper is a successful implementation of online ASM on FPGA for NIDS applications @cite_40 .