text: This article examines dynamic energy consumption caused by data during software execution on deeply embedded microprocessors, which can be significant on some devices. In worst-case energy consumption analysis, energy models are used to find the most costly execution path. Taking each instruction’s worst-case energy produces a safe but overly pessimistic upper bound. Algorithms for safe and tight bounds would be desirable. We show that finding exact worst-case energy is NP-hard, and that tight bounds cannot be approximated with guaranteed safety. We conclude that any energy model targeting tightness must either sacrifice safety or accept overapproximation proportional to data-dependent energy.
  @cite_14: The alignment of code in the flash memory of deeply embedded SoCs can have a large impact on the total energy consumption of a computation. We investigate the effect of code alignment in six SoCs and find that a large proportion of this energy (up to 15 of total SoC energy consumption) can be saved by changes to the alignment. A flexible model is created to predict the read-access energy consumption of flash memory on deeply embedded SoCs, where code is executed in place. This model uses the instruction level memory accesses performed by the processor to calculate the flash energy consumption of a sequence of instructions. We derive the model parameters for five SoCs and validate them. The error is as low as 5 , with a 11 average normalized RMS deviation overall. The scope for using this model to optimize code alignment is explored across a range of benchmarks and SoCs. Analysis shows that over 30 of loops can be better aligned. This can significantly reduce energy while increasing code size by less than 4 . We conclude that this effect has potential as an effective optimization, saving significant energy in deeply embedded SoCs.
  @cite_33: Dynamic power management in enterprise environments requires an understanding of the relationship between resource utilization and system-level power consumption. Power models based on resource utilization have been proposed in the context of enabling specific energy-efficiency optimizations on specific machines, but the accuracy and portability of different approaches to modeling have not been systematically compared. In this work, we use a common infrastructure to fit a family of high-level full-system power models, and we compare these models over a wide variation of workloads and machines, from a laptop to a server. This analysis shows that a model based on OS utilization metrics and CPU performance counters is generally most accurate across the machines and workloads tested. It is particularly useful for machines whose dynamic power consumption is not dominated by the CPU, as well as machines with aggressively power-managed CPUs, two classes of systems that are increasingly prevalent.
  @cite_23: We present a comprehensive high-level estimation framework for power consumed by the software in the processor caches. We demonstrate the framework on two types of caches commonly used in a modern day processor ARM1136 viz., L1 Data Cache and L2 Unified Cache. The major contribution of this paper is a linear energy model for the caches. The energy characterization starts with recognition of different types of operations in the caches. Further the energy of each operation is divided into sequential and non-sequential part depending on whether the operation is stand alone or happens in a burst with other operations. There is also an idle energy component of the cache since the cache may be inactive for considerable amount of time. The average error magnitude of the energy model when applied on the ARM1136 L1 Data Cache and L2 Unified Cache with a large suite of benchmarks is 1.7 , whereas the maximum error is less than 4.0 .
  @cite_39: DRAMs consume a large portion of total system energy consumption. Thus, reducing DRAM energy consumption is able to prolong the lifetime of battery-operated embedded portable systems. To this end, we propose DRAM energy-aware data prefetching scheme to lengthen DRAM idle periods by clustering DRAM accesses. Low-power modes of DRAMs can better exploit longer idle times. We performed experiments with a cycle-accurate simulator with built-in DRAM power model. The experimental results show that our proposed DRAM-aware prefetching is effective in reducing DRAM energy consumption. Up to 77 and average 59 of DRAM energy consumption is saved.
summary: Further modelling techniques for dynamic power go beyond the core part of the processor, such as analysing flash memory @cite_14 , caches @cite_23 and DRAMs @cite_39 . High performance processors feature hardware-provided counters that record metrics such as cache hit rates, which can be used by appropriately parametrised energy models @cite_33 . The energy consumption on the buses to these components can also be influenced by data values and can be modelled accordingly.