text: This article examines dynamic energy consumption caused by data during software execution on deeply embedded microprocessors, which can be significant on some devices. In worst-case energy consumption analysis, energy models are used to find the most costly execution path. Taking each instruction’s worst-case energy produces a safe but overly pessimistic upper bound. Algorithms for safe and tight bounds would be desirable. We show that finding exact worst-case energy is NP-hard, and that tight bounds cannot be approximated with guaranteed safety. We conclude that any energy model targeting tightness must either sacrifice safety or accept overapproximation proportional to data-dependent energy.
  @cite_28: Among the claims made concerning the advantages of asynchronous logic are that circuits can take advantage of average case (data dependent) speed rather than worst case speed. Whilst this argument can easily be sustained for a single logic stage its extension to systems consisting of many logic stages has not been widely investigated. This paper reports on investigations into the throughput of asynchronous and synchronous pipelines consisting of alternate latches and logic stages where the data dependent delay is a two valued random variable. The extent to which an average case speed of a single stage which is lower than worst case can be translated into higher throughput in an asynchronous pipeline as compared to a synchronous pipeline is found to be restricted by the coefficient of variation of the distribution of data dependent delay, the length of the pipeline, the number of latches used between each logic stage and the number data items in a loop.
summary: For the techniques that are used in WCET to be directly transferable to WCEC, a set amount of energy per operation would need to be specified and realised in hardware, similar to specifying and ensuring, through timing analysis at design time, that each operation fits into a fixed number of clock cycles. Consider the converse: A processor that presents a similar WCET analysis difficulty would be an asynchronous design, where the precise execution time is a non-trivial function of an operation's input data. Such devices may have an average delay, but actual performance or tight bounds for a given use case may be harder to determine @cite_28 .