Instruct: Identify the main and secondary category of Arxiv papers based on the titles and abstracts
Query: Efficient Post-Processors for Improving Error-Correcting Performance of
  LDPC Codes   The error floor phenomenon, associated with iterative decoders, is one of the
most significant limitations to the applications of low-density parity-check
(LDPC) codes. A variety of techniques from code design to decoder
implementation have been proposed to address the error floor problem, among
which post-processors have shown to be both effective and
implementation-friendly. In this work, we take the inspiration from simulated
annealing to generalize the post-processor design using three methods:
quenching, extended heating, and focused heating, each of which targets a
different error structure. The resulting post-processor is demonstrated to
lower the error floors by two orders of magnitude for two structured code
examples, a (2209, 1978) array LDPC code, and a (1944, 1620) LDPC code used by
the IEEE 802.11n standard. The post-processor can be integrated to a
belief-propagation decoder with minimal overhead. The post-processor design is
equally applicable to other structured LDPC codes.

5
The categories of this paper are: gr-qc
0
The categories of this paper are: hep-ph
11
The categories of this paper are: hep-lat
23
The categories of this paper are: solv-int
36
The categories of this paper are: cmp-lg
13
The categories of this paper are: quant-ph
6
The categories of this paper are: astro-ph
30
The categories of this paper are: q-alg
14
The categories of this paper are: math-ph
19
The categories of this paper are: eess
9
The categories of this paper are: nlin
18
The categories of this paper are: econ
8
The categories of this paper are: hep-ex
35
The categories of this paper are: mtrl-th
24
The categories of this paper are: dg-ga
37
The categories of this paper are: supr-con