Instruct: Identify the main and secondary category of Arxiv papers based on the titles and abstracts
Query: A simple 1-byte 1-clock RC4 design and its efficient implementation in
  FPGA coprocessor for secured ethernet communication   In the field of cryptography till date the 1-byte in 1-clock is the best
known RC4 hardware design [1], while the 1-byte in 3clocks is the best known
implementation [2,3]. The design algorithm in [1] considers two consecutive
bytes together and processes them in 2 clocks. The design of 1-byte in 3-clocks
is too much modular and clock hungry. In this paper considering the RC4
algorithm, as it is, a simpler RC4 hardware design providing higher throughput
is proposed in which 1-byte is processed in 1-clock. In the design two
sequential tasks are executed as two independent events during rising and
falling edges of the same clock and the swapping is directly executed using a
MUX-DEMUX combination. The power consumed in behavioral and structural designs
of RC4 are estimated and a power optimization technique is proposed. The NIST
statistical test suite is run on RC4 key streams in order to know its
randomness property. The encryption and decryption designs are respectively
embedded on two FPGA boards with RC4 in a custom coprocessor followed by
Ethernet communication.

21
The categories of this paper are: adap-org
16
The categories of this paper are: stat
27
The categories of this paper are: comp-gas
9
The categories of this paper are: nlin
37
The categories of this paper are: supr-con
17
The categories of this paper are: q-fin
13
The categories of this paper are: quant-ph
35
The categories of this paper are: mtrl-th
15
The categories of this paper are: nucl-ex
34
The categories of this paper are: chem-ph
2
The categories of this paper are: math
5
The categories of this paper are: gr-qc
12
The categories of this paper are: nucl-th
10
The categories of this paper are: q-bio
19
The categories of this paper are: eess
26
The categories of this paper are: bayes-an