Loads the contents of memory location M into the designated register.

        source code forms: LDA P; LDB P

        CC bits "HNZVC": -aa0-
354667
def instruction_LD8(self, opcode, m, register):
        
#        log.debug("$%x LD8 %s = $%x" % (
#            self.program_counter,
#            register.name, m,
#        ))
        register.set(m)
        self.clear_NZV()
        self.update_NZ_8(m)
1080532
public void init_decod_ld8k()
	{
	    /* Initialize static pointer */
	    exc    = 0 + LD8KConstants.PIT_MAX + LD8KConstants.L_INTERPOL;

	    /* Static vectors to zero */
	    Util.set_zero(old_exc_array,LD8KConstants.PIT_MAX + LD8KConstants.L_INTERPOL);
	    Util.set_zero(mem_syn, LD8KConstants.M);

	    sharp = LD8KConstants.SHARPMIN;
	    old_t0 = 60;
	    gain_code.value = (float)0.;
	    gain_pitch.value = (float)0.;

	    lspDec.lsp_decw_reset();

	    return;
	}
217472
def _pstore16(ins):
    
    value = ins.quad[2]
    offset = ins.quad[1]
    indirect = offset[0] == '*'
    size = 1
    if indirect:
        offset = offset[1:]

    I = int(offset)
    if I >= 0:
        I += 4  # Return Address + "push IX"

    if is_int(value):
        output = []
    else:
        output = _16bit_oper(value)

    ix_changed = not (-128 + size <= I <= 127 - size)  # Offset > 127 bytes. Need to change IX

    if indirect:
        if is_int(value):
            output.append('ld hl, %i' % int16(value))

        output.append('ld bc, %i' % I)
        output.append('call __PISTORE16')
        REQUIRES.add('istore16.asm')
        return output

    # direct store
    if ix_changed:  # more than 1 byte
        if not is_int(value):
            output.append('ex de, hl')

        output.append('push ix')
        output.append('pop hl')
        output.append('ld bc, %i' % I)
        output.append('add hl, bc')

        if is_int(value):
            v = int16(value)
            output.append('ld (hl), %i' % (v & 0xFF))
            output.append('inc hl')
            output.append('ld (hl), %i' % (v >> 8))
            return output
        else:
            output.append('ld (hl), e')
            output.append('inc hl')
            output.append('ld (hl), d')
            return output

    if is_int(value):
        v = int16(value)
        output.append('ld (ix%+i), %i' % (I, v & 0xFF))
        output.append('ld (ix%+i), %i' % (I + 1, v >> 8))
    else:
        output.append('ld (ix%+i), l' % I)
        output.append('ld (ix%+i), h' % (I + 1))

    return output
1291240
def _lsm_load_pages(self):
        """"""
        # cache all pages to preserve corrected values
        pages = self.pages
        pages.cache = True
        pages.useframes = True
        # use first and second page as keyframes
        pages.keyframe = 1
        pages.keyframe = 0
        # load remaining pages as frames
        pages._load(keyframe=None)
        # fix offsets and bytecounts first
        self._lsm_fix_strip_offsets()
        self._lsm_fix_strip_bytecounts()
        # assign keyframes for data and thumbnail series
        keyframe = pages[0]
        for page in pages[::2]:
            page.keyframe = keyframe
        keyframe = pages[1]
        for page in pages[1::2]:
            page.keyframe = keyframe
1357809
def read_core_registers_raw(self, reg_list):
        
        # convert to index only
        reg_list = [register_name_to_index(reg) for reg in reg_list]

        # Sanity check register values
        for reg in reg_list:
            if reg not in CORE_REGISTER.values():
                raise ValueError("unknown reg: %d" % reg)
            elif is_fpu_register(reg) and (not self.has_fpu):
                raise ValueError("attempt to read FPU register without FPU")

        # Handle doubles.
        doubles = [reg for reg in reg_list if is_double_float_register(reg)]
        hasDoubles = len(doubles) > 0
        if hasDoubles:
            originalRegList = reg_list
            
            # Strip doubles from reg_list.
            reg_list = [reg for reg in reg_list if not is_double_float_register(reg)]
            
            # Read float regs required to build doubles.
            singleRegList = []
            for reg in doubles:
                singleRegList += (-reg, -reg + 1)
            singleValues = self.read_core_registers_raw(singleRegList)

        # Begin all reads and writes
        dhcsr_cb_list = []
        reg_cb_list = []
        for reg in reg_list:
            if is_cfbp_subregister(reg):
                reg = CORE_REGISTER['cfbp']
            elif is_psr_subregister(reg):
                reg = CORE_REGISTER['xpsr']

            # write id in DCRSR
            self.write_memory(CortexM.DCRSR, reg)

            # Technically, we need to poll S_REGRDY in DHCSR here before reading DCRDR. But
            # we're running so slow compared to the target that it's not necessary.
            # Read it and assert that S_REGRDY is set

            dhcsr_cb = self.read_memory(CortexM.DHCSR, now=False)
            reg_cb = self.read_memory(CortexM.DCRDR, now=False)
            dhcsr_cb_list.append(dhcsr_cb)
            reg_cb_list.append(reg_cb)

        # Read all results
        reg_vals = []
        for reg, reg_cb, dhcsr_cb in zip(reg_list, reg_cb_list, dhcsr_cb_list):
            dhcsr_val = dhcsr_cb()
            assert dhcsr_val & CortexM.S_REGRDY
            val = reg_cb()

            # Special handling for registers that are combined into a single DCRSR number.
            if is_cfbp_subregister(reg):
                val = (val >> ((-reg - 1) * 8)) & 0xff
            elif is_psr_subregister(reg):
                val &= sysm_to_psr_mask(reg)

            reg_vals.append(val)
        
        # Merge double regs back into result list.
        if hasDoubles:
            results = []
            for reg in originalRegList:
                # Double
                if is_double_float_register(reg):
                    doubleIndex = doubles.index(reg)
                    singleLow = singleValues[doubleIndex * 2]
                    singleHigh = singleValues[doubleIndex * 2 + 1]
                    double = (singleHigh << 32) | singleLow
                    results.append(double)
                # Other register
                else:
                    results.append(reg_vals[reg_list.index(reg)])
            reg_vals = results

        return reg_vals
62909
def _read_register(self, reg):
        """"""
        self.buf[0] = reg
        with self.i2c_device as i2c:
            i2c.write(self.buf, end=1, stop=False)
            i2c.readinto(self.buf, end=2)
        return self.buf[0] << 8 | self.buf[1]
444310
def set_register_context(self, data):
        
        logging.debug("GDB setting register context")
        reg_num_list = []
        reg_data_list = []
        for reg in self._register_list:
            if reg.bitsize == 64:
                regValue = conversion.hex16_to_u64be(data)
                data = data[16:]
            else:
                regValue = conversion.hex8_to_u32be(data)
                data = data[8:]
            reg_num_list.append(reg.reg_num)
            reg_data_list.append(regValue)
            logging.debug("GDB reg: %s = 0x%X", reg.name, regValue)
        self._context.write_core_registers_raw(reg_num_list, reg_data_list)
107717
def _load_entries(self, root):
        """"""
        mdict = {
            "comments": self._comment,
            "line": self._line,
            "group": self._group
        }
        for entry in root:
            mdict[entry.tag](entry)
465761
def get_register_context(self):
        
        logging.debug("GDB getting register context")
        resp = b''
        reg_num_list = [reg.reg_num for reg in self._register_list]
        vals = self._context.read_core_registers_raw(reg_num_list)
        #print("Vals: %s" % vals)
        for reg, regValue in zip(self._register_list, vals):
            if reg.bitsize == 64:
                resp += six.b(conversion.u64_to_hex16le(regValue))
            else:
                resp += six.b(conversion.u32_to_hex8le(regValue))
            logging.debug("GDB reg: %s = 0x%X", reg.name, regValue)

        return resp
936520
def __execute_ldm(self, instr):
        
        assert instr.operands[0].size == self.__mem.address_size
        assert instr.operands[2].size in [8, 16, 32, 64, 128, 256]

        # Memory address.
        op0_val = self.read_operand(instr.operands[0])
        # Data.
        op2_val = self.read_memory(op0_val, instr.operands[2].size // 8)

        self.write_operand(instr.operands[2], op2_val)

        return None
304509
def _get_constrs_load_memory(self, gadget):
        
        dst = self.analyzer.get_register_expr(gadget.destination[0].name, mode="post")
        size = gadget.destination[0].size

        if isinstance(gadget.sources[0], ReilRegisterOperand):
            base_addr = self.analyzer.get_register_expr(gadget.sources[0].name, mode="pre")
            offset = gadget.sources[1].immediate

            addr = base_addr + offset
        else:
            addr = gadget.sources[1].immediate

        constrs = []

        for i in reversed(range(0, size, 8)):
            bytes_exprs_1 = self.analyzer.get_memory_expr(addr + i // 8, 8 // 8)
            bytes_exprs_2 = smtfunction.extract(dst, i, 8)

            constrs += [bytes_exprs_1 != bytes_exprs_2]

        # Check all non-modified registers don't change.
        constrs_mod = []

        for name in self._arch_info.registers_gp_base:
            if name not in [r.name for r in gadget.modified_registers]:
                var_initial = self.analyzer.get_register_expr(name, mode="pre")
                var_final = self.analyzer.get_register_expr(name, mode="post")

                constrs_mod += [var_initial != var_final]

        if constrs_mod:
            constrs_mod = [reduce(lambda c, acc: acc | c, constrs_mod[1:], constrs_mod[0])]

        return constrs + constrs_mod
483238
def _compute_memory_address(self, mem_operand):
        
        base = ReilRegisterOperand(mem_operand.base_reg.name, mem_operand.size)

        if mem_operand.displacement:
            address = self.temporal(mem_operand.size)

            if isinstance(mem_operand.displacement, ArmRegisterOperand):
                disp = ReilRegisterOperand(mem_operand.displacement.name, mem_operand.size)
            elif isinstance(mem_operand.displacement, ArmImmediateOperand):
                disp = ReilImmediateOperand(mem_operand.displacement.immediate, mem_operand.size)
            elif isinstance(mem_operand.displacement, ArmShiftedRegisterOperand):
                disp = self._compute_shifted_register(mem_operand.displacement)
            else:
                raise Exception("_compute_memory_address: displacement type unknown")

            if mem_operand.index_type == ARM_MEMORY_INDEX_PRE:
                if mem_operand.disp_minus:
                    self.add(self._builder.gen_sub(base, disp, address))
                else:
                    self.add(self._builder.gen_add(base, disp, address))
                self.add(self._builder.gen_str(address, base))
            elif mem_operand.index_type == ARM_MEMORY_INDEX_OFFSET:
                if mem_operand.disp_minus:
                    self.add(self._builder.gen_sub(base, disp, address))
                else:
                    self.add(self._builder.gen_add(base, disp, address))
            elif mem_operand.index_type == ARM_MEMORY_INDEX_POST:
                self.add(self._builder.gen_str(base, address))
                tmp = self.temporal(base.size)
                if mem_operand.disp_minus:
                    self.add(self._builder.gen_sub(base, disp, tmp))
                else:
                    self.add(self._builder.gen_add(base, disp, tmp))
                self.add(self._builder.gen_str(tmp, base))
            else:
                raise Exception("_compute_memory_address: indexing type unknown")

        else:
            address = base

        return address
781456
def load(self, ptr, name='', align=None):
        
        if not isinstance(ptr.type, types.PointerType):
            raise TypeError("cannot load from value of type %s (%r): not a pointer"
                            % (ptr.type, str(ptr)))
        ld = instructions.LoadInstr(self.block, ptr, name)
        ld.align = align
        self._insert(ld)
        return ld
652008
def instruction_OR(self, opcode, m, register):
        
        a = register.value
        r = a | m
        register.set(r)
        self.clear_NZV()
        self.update_NZ_8(r)
535665
def memory_map(self):
        
        return '\n'.join(sorted("%04X: %s" % (x.value, x.name) for x in self.global_labels.values() if x.is_address))
506798
def _aload16(ins):
    ''' 
    '''
    output = _addr(ins.quad[2])

    output.append('ld e, (hl)')
    output.append('inc hl')
    output.append('ld d, (hl)')
    output.append('ex de, hl')
    output.append('push hl')

    return output
1058308
private void setBitsImpl(int position, long value, int length) {
		int i = position >> ADDRESS_BITS;
		int s = position & ADDRESS_MASK;
		long m = length == ADDRESS_SIZE ? -1L : (1L << length) - 1L;
		long v = value & m;
		performAdjSet(length, i, s, m, v);
	}