Returns operands of an ASM instruction.
    Even "indirect" operands, like SP if RET or CALL is used.
341880
def oper(inst):
    
    i = inst.strip(' \t\n').split(' ')
    I = i[0].lower()  # Instruction
    i = ''.join(i[1:])

    op = i.split(',')
    if I in {'call', 'jp', 'jr'} and len(op) > 1:
        op = op[1:] + ['f']

    elif I == 'djnz':
        op.append('b')

    elif I in {'push', 'pop', 'call'}:
        op.append('sp')  # Sp is also affected by push, pop and call

    elif I in {'or', 'and', 'xor', 'neg', 'cpl', 'rrca', 'rlca'}:
        op.append('a')

    elif I in {'rra', 'rla'}:
        op.extend(['a', 'f'])

    elif I in ('rr', 'rl'):
        op.append('f')

    elif I in {'adc', 'sbc'}:
        if len(op) == 1:
            op = ['a', 'f'] + op

    elif I in {'add', 'sub'}:
        if len(op) == 1:
            op = ['a'] + op

    elif I in {'ldd', 'ldi', 'lddr', 'ldir'}:
        op = ['hl', 'de', 'bc']

    elif I in {'cpd', 'cpi', 'cpdr', 'cpir'}:
        op = ['a', 'hl', 'bc']

    elif I == 'exx':
        op = ['*', 'bc', 'de', 'hl', 'b', 'c', 'd', 'e', 'h', 'l']

    elif I in {'ret', 'reti', 'retn'}:
        op += ['sp']

    elif I == 'out':
        if len(op) and RE_OUTC.match(op[0]):
            op[0] = 'c'
        else:
            op.pop(0)

    elif I == 'in':
        if len(op) > 1 and RE_OUTC.match(op[1]):
            op[1] = 'c'
        else:
            op.pop(1)

    for i in range(len(op)):
        tmp = RE_INDIR16.match(op[i])
        if tmp is not None:
            op[i] = '(' + op[i].strip()[1:-1].strip().lower() + ')'  # '  (  dE )  ' => '(de)'

    return op
1328131
def opers(self):
        
        i = [x for x in self.asm.strip(' \t\n').split(' ') if x != '']

        if len(i) == 1:
            return []

        i = ''.join(i[1:]).split(',')
        if self.condition_flag is not None:
            i = i[1:]
        else:
            i = i[0:]

        op = [x.lower() if is_register(x) else x for x in i]
        return op
1362518
def _astore32(ins):
    ''' 
    '''
    output = _addr(ins.quad[1])

    value = ins.quad[2]
    if value[0] == '*':
        value = value[1:]
        indirect = True
    else:
        indirect = False

    try:
        value = int(ins.quad[2]) & 0xFFFFFFFF  # Immediate?
        if indirect:
            output.append('push hl')
            output.append('ld hl, %i' % (value & 0xFFFF))
            output.append('call __ILOAD32')
            output.append('ld b, h')
            output.append('ld c, l')  # BC = Lower 16 bits
            output.append('pop hl')
            REQUIRES.add('iload32.asm')
        else:
            output.append('ld de, %i' % (value >> 16))
            output.append('ld bc, %i' % (value & 0xFFFF))
    except ValueError:
        output.append('pop bc')
        output.append('pop de')

    output.append('call __STORE32')
    REQUIRES.add('store32.asm')

    return output
555531
def _and32(ins):
    
    op1, op2 = tuple(ins.quad[2:])

    if _int_ops(op1, op2):
        op1, op2 = _int_ops(op1, op2)

        if op2 == 0:  # X and False = False
            if str(op1)[0] == 't':  # a temporary term (stack)
                output = _32bit_oper(op1)  # Remove op1 from the stack
            else:
                output = []
            output.append('xor a')
            output.append('push af')
            return output

            # For X and TRUE = X we do nothing as we have to convert it to boolean
            # which is a rather expensive instruction

    output = _32bit_oper(op1, op2)
    output.append('call __AND32')
    output.append('push af')
    REQUIRES.add('and32.asm')
    return output
1324158
def instruction_addresses(self):
        
        if self._instruction_addresses is None:
            if self.statements is None:
                self._instruction_addresses = [ ]
            else:
                self._instruction_addresses = [ (s.addr + s.delta) for s in self.statements if type(s) is stmt.IMark ]
        return self._instruction_addresses
275807
def arithmetic(self, operation, operand1, operand2, operand3 = None):
        
        if isinstance(operand1, int):
            output_type = self.symtab.get_type(operand1)
            self.free_if_register(operand1)
        else:
            output_type = None
        if isinstance(operand2, int):
            output_type = self.symtab.get_type(operand2) if output_type == None else output_type
            self.free_if_register(operand2)
        else:
            output_type = SharedData.TYPES.NO_TYPE if output_type == None else output_type
        #if operand3 is not defined, reserve one free register for it
        output = self.take_register(output_type) if operand3 == None else operand3
        mnemonic = self.arithmetic_mnemonic(operation, output_type)
        self.newline_text("{0}\t{1},{2},{3}".format(mnemonic, self.symbol(operand1), self.symbol(operand2), self.symbol(output)), True)
        return output
1265905
def single_registers(op):
    
    result = set()
    if isinstance(op, str):
        op = [op]

    for x in op:
        if is_8bit_register(x):
            result = result.union([x])
        elif x == 'sp':
            result.add(x)
        elif x == 'af':
            result = result.union(['a', 'f'])
        elif x == "af'":
            result = result.union(["a'", "f'"])
        elif is_16bit_register(x):  # Must be a 16bit reg or we have an internal error!
            result = result.union([LO16(x), HI16(x)])

    return list(result)
1335821
function disasm1(machine_code, offset=0) {
  let di = decode_instruction(machine_code[offset]);

  let opcode, operand;
  let consumed = 1; // 1-tryte opcode, incremented later if operands

  if (di.family === 0) {
    opcode = invertKv(OP)[di.operation]; // inefficient lookup, but probably doesn't matter

    // note: some duplication with cpu read_alu_operand TODO: factor out
    // TODO: handle reading beyond end
    let decoded_operand = decode_operand(di, machine_code, offset);
    operand = stringify_operand(decoded_operand);
    consumed += decoded_operand.consumed;
  } else if (di.family === 1) {
    opcode = 'BR';
    opcode += invertKv(FLAGS)[di.flag];
    opcode += {'-1':'L', 0:'E', 1:'N'}[di.direction];
    opcode += {'-1':'N', 0:'Z', 1:'P'}[di.compare];

    if (invertKv(BRANCH_INSTRUCTION_SHORTHANDS)[opcode]) {
      // prefer the shorthand if there is one (BRSEZ -> BEQ)
      opcode = invertKv(BRANCH_INSTRUCTION_SHORTHANDS)[opcode];
    }

    let rel_address = machine_code[offset + 1];
    if (rel_address === undefined) {
      operand = '???'
    } else {
      if (rel_address > 0) {
        // always add +, since makes relativity clearer
        operand = '#+' + rel_address.toString();
      } else {
        operand = '#' + rel_address.toString();
      }
    }

    consumed += 1;
  } else if (di.family === -1) {
    opcode = invertKv(XOP)[di.operation];
    // TODO: undefined opcodes

    let decoded_operand = decode_operand(di, machine_code, offset);
    operand = stringify_operand(decoded_operand);
    consumed += decoded_operand.consumed;

    console.log('XOP di.operation',di.operation,XOP_TO_ADDR_MODE[di.operation]);
    if (XOP_TO_ADDR_MODE[opcode] !== undefined) {
      // some extended opcodes can disassemble to alu special addressing modes
      opcode = xop_operation_to_assembly_opcode_string(opcode);
    }
  }

  let asm;

  if (operand !== undefined) {
    asm = opcode + ' ' + operand;
  } else {
    asm = opcode;
  }

  return {asm, consumed};
}
291424
def _addr(value):
    ''' 
    '''
    output = []

    try:
        indirect = False
        if value[0] == '*':
            indirect = True
            value = value[1:]

        value = int(value) & 0xFFFF
        if indirect:
            output.append('ld hl, (%s)' % str(value))
        else:
            output.append('ld hl, %s' % str(value))

    except ValueError:
        if value[0] == '_':
            output.append('ld hl, %s' % str(value))
            if indirect:
                output.append('ld c, (hl)')
                output.append('inc hl')
                output.append('ld h, (hl)')
                output.append('ld l, c')
        else:
            output.append('pop hl')
            if indirect:
                output.append('ld c, (hl)')
                output.append('inc hl')
                output.append('ld h, (hl)')
                output.append('ld l, c')

    output.append('call __ARRAY')
    REQUIRES.add('array.asm')

    return output
748147
def _get_constrs_arithmetic(self, gadget):
        
        # *dst* register has to have the value of *src1 op src2* for all
        # possibles assignments of *src1* and *src2*.

        dst = self.analyzer.get_register_expr(gadget.destination[0].name, mode="post")
        src1 = self.analyzer.get_register_expr(gadget.sources[0].name, mode="pre")
        src2 = self.analyzer.get_register_expr(gadget.sources[1].name, mode="pre")
        op = self._arithmetic_ops[gadget.operation]

        # Check all non-modified registers don't change.
        constrs_mod = []

        for name in self._arch_info.registers_gp_base:
            if name not in [r.name for r in gadget.modified_registers]:
                var_initial = self.analyzer.get_register_expr(name, mode="pre")
                var_final = self.analyzer.get_register_expr(name, mode="post")

                constrs_mod += [var_initial != var_final]

        if constrs_mod:
            constrs_mod = [reduce(lambda c, acc: acc | c, constrs_mod[1:], constrs_mod[0])]

        return [dst != op(src1, src2)] + constrs_mod
1007595
def __get_instructions(self):
        ""
        if self.mode == 'c':
            c, m = utils.recv(self.__s)
            inst = [(c, m, self.__s)]
        else:
            inst = []
            with self.__client_list_lock:
                for com in self.clients:
                    c, m = utils.recv(com)
                    if c is not None:
                        inst.append((c, m, com))
        return inst
1058731
def _ret16(ins):
    
    output = _16bit_oper(ins.quad[1])
    output.append('#pragma opt require hl')
    output.append('jp %s' % str(ins.quad[2]))
    return output
161934
def _get_actual_addrs(action, state):
        

        if action.actual_addrs is None:
            # For now, mem reads don't necessarily have actual_addrs set properly
            try:
                addr_list = {state.solver.eval(action.addr.ast)}
            except (SimSolverModeError, SimUnsatError, ZeroDivisionError):
                # FIXME: ZeroDivisionError should have been caught by claripy and simuvex.
                # FIXME: see claripy issue #75. this is just a temporary workaround.
                # it's symbolic... just continue
                addr_list = {0x60000000}  # TODO: this is a random address that I pick. Fix it.
        else:
            addr_list = set(action.actual_addrs)

        return addr_list
1067768
def reg(self):
        """"""
        if self.type.is_displ or self.type.is_phrase:
            size = core.get_native_size()
            return base.get_register_name(self.reg_id, size)

        if self.type.is_reg:
            return base.get_register_name(self.reg_id, self.size)

        else:
            raise exceptions.SarkOperandWithoutReg("Operand does not have a register.")
706527
def execute(self, asm_instr):
        
        # Update the instruction pointer.
        self.ir_emulator.registers[self.ip] = asm_instr.address + asm_instr.size

        # Process syscall.
        if self.arch_info.instr_is_syscall(asm_instr):
            raise Syscall()

        # Process instruction and return next address instruction to execute.
        return self.__execute(asm_instr)
170080
def instruction_PAGE(self, opcode):
        
        op_address, opcode2 = self.read_pc_byte()
        paged_opcode = opcode * 256 + opcode2
#        log.debug("$%x *** call paged opcode $%x" % (
#            self.program_counter, paged_opcode
#        ))
        self.call_instruction_func(op_address - 1, paged_opcode)
1050038
def asm(self, ftype, asm, constraint, args, side_effect, name=''):
        
        asm = instructions.InlineAsm(ftype, asm, constraint, side_effect)
        return self.call(asm, args, name)