code:
// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later

#include "shader_recompiler/frontend/ir/program.h"
#include "shader_recompiler/ir_opt/passes.h"

namespace Shader::Optimization {

void ConditionalBarrierPass(IR::Program& program) {
    s32 conditional_control_flow_count{0};
    s32 conditional_return_count{0};
    for (IR::AbstractSyntaxNode& node : program.syntax_list) {
        switch (node.type) {
        case IR::AbstractSyntaxNode::Type::If:
        case IR::AbstractSyntaxNode::Type::Loop:
            conditional_control_flow_count++;
            break;
        case IR::AbstractSyntaxNode::Type::EndIf:
        case IR::AbstractSyntaxNode::Type::Repeat:
            conditional_control_flow_count--;
            break;
        case IR::AbstractSyntaxNode::Type::Unreachable:
        case IR::AbstractSyntaxNode::Type::Return:
            if (conditional_control_flow_count > 0) {
                conditional_return_count++;
            }
            break;
        case IR::AbstractSyntaxNode::Type::Block:
            for (IR::Inst& inst : node.data.block->Instructions()) {
                if ((conditional_control_flow_count > 0 || conditional_return_count > 0) &&
                    inst.GetOpcode() == IR::Opcode::Barrier) {
                    LOG_WARNING(Shader, "Barrier within conditional control flow");
                    inst.ReplaceOpcode(IR::Opcode::Identity);
                }
            }
            break;
        default:
            break;
        }
    }
    ASSERT(conditional_control_flow_count == 0);
}

} // namespace Shader::Optimization


code:
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later

#include <algorithm>
#include <functional>
#include <tuple>
#include <type_traits>

#include "common/bit_cast.h"
#include "shader_recompiler/environment.h"
#include "shader_recompiler/exception.h"
#include "shader_recompiler/frontend/ir/ir_emitter.h"
#include "shader_recompiler/frontend/ir/modifiers.h"
#include "shader_recompiler/frontend/ir/value.h"
#include "shader_recompiler/ir_opt/passes.h"

namespace Shader::Optimization {
namespace {
// Metaprogramming stuff to get arguments information out of a lambda
template <typename Func>
struct LambdaTraits : LambdaTraits<decltype(&std::remove_reference_t<Func>::operator())> {};

template <typename ReturnType, typename LambdaType, typename... Args>
struct LambdaTraits<ReturnType (LambdaType::*)(Args...) const> {
    template <size_t I>
    using ArgType = std::tuple_element_t<I, std::tuple<Args...>>;

    static constexpr size_t NUM_ARGS{sizeof...(Args)};
};

template <typename T>
[[nodiscard]] T Arg(const IR::Value& value) {
    if constexpr (std::is_same_v<T, bool>) {
        return value.U1();
    } else if constexpr (std::is_same_v<T, u32>) {
        return value.U32();
    } else if constexpr (std::is_same_v<T, s32>) {
        return static_cast<s32>(value.U32());
    } else if constexpr (std::is_same_v<T, f32>) {
        return value.F32();
    } else if constexpr (std::is_same_v<T, u64>) {
        return value.U64();
    }
}

template <typename T, typename ImmFn>
bool FoldCommutative(IR::Inst& inst, ImmFn&& imm_fn) {
    const IR::Value lhs{inst.Arg(0)};
    const IR::Value rhs{inst.Arg(1)};

    const bool is_lhs_immediate{lhs.IsImmediate()};
    const bool is_rhs_immediate{rhs.IsImmediate()};

    if (is_lhs_immediate && is_rhs_immediate) {
        const auto result{imm_fn(Arg<T>(lhs), Arg<T>(rhs))};
        inst.ReplaceUsesWith(IR::Value{result});
        return false;
    }
    if (is_lhs_immediate && !is_rhs_immediate) {
        IR::Inst* const rhs_inst{rhs.InstRecursive()};
        if (rhs_inst->GetOpcode() == inst.GetOpcode() && rhs_inst->Arg(1).IsImmediate()) {
            const auto combined{imm_fn(Arg<T>(lhs), Arg<T>(rhs_inst->Arg(1)))};
            inst.SetArg(0, rhs_inst->Arg(0));
            inst.SetArg(1, IR::Value{combined});
        } else {
            // Normalize
            inst.SetArg(0, rhs);
            inst.SetArg(1, lhs);
        }
    }
    if (!is_lhs_immediate && is_rhs_immediate) {
        const IR::Inst* const lhs_inst{lhs.InstRecursive()};
        if (lhs_inst->GetOpcode() == inst.GetOpcode() && lhs_inst->Arg(1).IsImmediate()) {
            const auto combined{imm_fn(Arg<T>(rhs), Arg<T>(lhs_inst->Arg(1)))};
            inst.SetArg(0, lhs_inst->Arg(0));
            inst.SetArg(1, IR::Value{combined});
        }
    }
    return true;
}

template <typename Func>
bool FoldWhenAllImmediates(IR::Inst& inst, Func&& func) {
    if (!inst.AreAllArgsImmediates() || inst.HasAssociatedPseudoOperation()) {
        return false;
    }
    using Indices = std::make_index_sequence<LambdaTraits<decltype(func)>::NUM_ARGS>;
    inst.ReplaceUsesWith(EvalImmediates(inst, func, Indices{}));
    return true;
}

/// Return true when all values in a range are equal
template <typename Range>
bool AreEqual(const Range& range) {
    auto resolver{[](const auto& value) { return value.Resolve(); }};
    auto equal{[](const IR::Value& lhs, const IR::Value& rhs) {
        if (lhs == rhs) {
            return true;
        }
        // Not equal, but try to match if they read the same constant buffer
        if (!lhs.IsImmediate() && !rhs.IsImmediate() &&
            lhs.Inst()->GetOpcode() == IR::Opcode::GetCbufU32 &&
            rhs.Inst()->GetOpcode() == IR::Opcode::GetCbufU32 &&
            lhs.Inst()->Arg(0) == rhs.Inst()->Arg(0) && lhs.Inst()->Arg(1) == rhs.Inst()->Arg(1)) {
            return true;
        }
        return false;
    }};
    return std::ranges::adjacent_find(range, std::not_fn(equal), resolver) == std::end(range);
}

void FoldGetRegister(IR::Inst& inst) {
    if (inst.Arg(0).Reg() == IR::Reg::RZ) {
        inst.ReplaceUsesWith(IR::Value{u32{0}});
    }
}

void FoldGetPred(IR::Inst& inst) {
    if (inst.Arg(0).Pred() == IR::Pred::PT) {
        inst.ReplaceUsesWith(IR::Value{true});
    }
}

/// Replaces the XMAD pattern generated by an integer FMA
bool FoldXmadMultiplyAdd(IR::Block& block, IR::Inst& inst) {
    /*
     * We are looking for this specific pattern:
     *   %6      = BitFieldUExtract %op_b, #0, #16
     *   %7      = BitFieldUExtract %op_a', #16, #16
     *   %8      = IMul32 %6, %7
     *   %10     = BitFieldUExtract %op_a', #0, #16
     *   %11     = BitFieldInsert %8, %10, #16, #16
     *   %15     = BitFieldUExtract %op_b, #0, #16
     *   %16     = BitFieldUExtract %op_a, #0, #16
     *   %17     = IMul32 %15, %16
     *   %18     = IAdd32 %17, %op_c
     *   %22     = BitFieldUExtract %op_b, #16, #16
     *   %23     = BitFieldUExtract %11, #16, #16
     *   %24     = IMul32 %22, %23
     *   %25     = ShiftLeftLogical32 %24, #16
     *   %26     = ShiftLeftLogical32 %11, #16
     *   %27     = IAdd32 %26, %18
     *   %result = IAdd32 %25, %27
     *
     * And replace it with:
     *  %temp   = IMul32 %op_a, %op_b
     *  %result = IAdd32 %temp, %op_c
     *
     * This optimization has been proven safe by Nvidia's compiler logic being reversed.
     * (If Nvidia generates this code from 'fma(a, b, c)', we can do the same in the reverse order.)
     */
    const IR::Value zero{0u};
    const IR::Value sixteen{16u};
    IR::Inst* const _25{inst.Arg(0).TryInstRecursive()};
    IR::Inst* const _27{inst.Arg(1).TryInstRecursive()};
    if (!_25 || !_27) {
        return false;
    }
    if (_27->GetOpcode() != IR::Opcode::IAdd32) {
        return false;
    }
    if (_25->GetOpcode() != IR::Opcode::ShiftLeftLogical32 || _25->Arg(1) != sixteen) {
        return false;
    }
    IR::Inst* const _24{_25->Arg(0).TryInstRecursive()};
    if (!_24 || _24->GetOpcode() != IR::Opcode::IMul32) {
        return false;
    }
    IR::Inst* const _22{_24->Arg(0).TryInstRecursive()};
    IR::Inst* const _23{_24->Arg(1).TryInstRecursive()};
    if (!_22 || !_23) {
        return false;
    }
    if (_22->GetOpcode() != IR::Opcode::BitFieldUExtract) {
        return false;
    }
    if (_23->GetOpcode() != IR::Opcode::BitFieldUExtract) {
        return false;
    }
    if (_22->Arg(1) != sixteen || _22->Arg(2) != sixteen) {
        return false;
    }
    if (_23->Arg(1) != sixteen || _23->Arg(2) != sixteen) {
        return false;
    }
    IR::Inst* const _11{_23->Arg(0).TryInstRecursive()};
    if (!_11 || _11->GetOpcode() != IR::Opcode::BitFieldInsert) {
        return false;
    }
    if (_11->Arg(2) != sixteen || _11->Arg(3) != sixteen) {
        return false;
    }
    IR::Inst* const _8{_11->Arg(0).TryInstRecursive()};
    IR::Inst* const _10{_11->Arg(1).TryInstRecursive()};
    if (!_8 || !_10) {
        return false;
    }
    if (_8->GetOpcode() != IR::Opcode::IMul32) {
        return false;
    }
    if (_10->GetOpcode() != IR::Opcode::BitFieldUExtract) {
        return false;
    }
    IR::Inst* const _6{_8->Arg(0).TryInstRecursive()};
    IR::Inst* const _7{_8->Arg(1).TryInstRecursive()};
    if (!_6 || !_7) {
        return false;
    }
    if (_6->GetOpcode() != IR::Opcode::BitFieldUExtract) {
        return false;
    }
    if (_7->GetOpcode() != IR::Opcode::BitFieldUExtract) {
        return false;
    }
    if (_6->Arg(1) != zero || _6->Arg(2) != sixteen) {
        return false;
    }
    if (_7->Arg(1) != sixteen || _7->Arg(2) != sixteen) {
        return false;
    }
    IR::Inst* const _26{_27->Arg(0).TryInstRecursive()};
    IR::Inst* const _18{_27->Arg(1).TryInstRecursive()};
    if (!_26 || !_18) {
        return false;
    }
    if (_26->GetOpcode() != IR::Opcode::ShiftLeftLogical32 || _26->Arg(1) != sixteen) {
        return false;
    }
    if (_26->Arg(0).InstRecursive() != _11) {
        return false;
    }
    if (_18->GetOpcode() != IR::Opcode::IAdd32) {
        return false;
    }
    IR::Inst* const _17{_18->Arg(0).TryInstRecursive()};
    if (!_17 || _17->GetOpcode() != IR::Opcode::IMul32) {
        return false;
    }
    IR::Inst* const _15{_17->Arg(0).TryInstRecursive()};
    IR::Inst* const _16{_17->Arg(1).TryInstRecursive()};
    if (!_15 || !_16) {
        return false;
    }
    if (_15->GetOpcode() != IR::Opcode::BitFieldUExtract) {
        return false;
    }
    if (_16->GetOpcode() != IR::Opcode::BitFieldUExtract) {
        return false;
    }
    if (_15->Arg(1) != zero || _16->Arg(1) != zero || _10->Arg(1) != zero) {
        return false;
    }
    if (_15->Arg(2) != sixteen || _16->Arg(2) != sixteen || _10->Arg(2) != sixteen) {
        return false;
    }
    const std::array<IR::Value, 3> op_as{
        _7->Arg(0).Resolve(),
        _16->Arg(0).Resolve(),
        _10->Arg(0).Resolve(),
    };
    const std::array<IR::Value, 3> op_bs{
        _22->Arg(0).Resolve(),
        _6->Arg(0).Resolve(),
        _15->Arg(0).Resolve(),
    };
    const IR::U32 op_c{_18->Arg(1)};
    if (!AreEqual(op_as) || !AreEqual(op_bs)) {
        return false;
    }
    IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
    inst.ReplaceUsesWith(ir.IAdd(ir.IMul(IR::U32{op_as[0]}, IR::U32{op_bs[1]}), op_c));
    return true;
}

/// Replaces the pattern generated by two XMAD multiplications
bool FoldXmadMultiply(IR::Block& block, IR::Inst& inst) {
    /*
     * We are looking for this pattern:
     *   %rhs_bfe = BitFieldUExtract %factor_a, #0, #16
     *   %rhs_mul = IMul32 %rhs_bfe, %factor_b
     *   %lhs_bfe = BitFieldUExtract %factor_a, #16, #16
     *   %rhs_mul = IMul32 %lhs_bfe, %factor_b
     *   %lhs_shl = ShiftLeftLogical32 %rhs_mul, #16
     *   %result  = IAdd32 %lhs_shl, %rhs_mul
     *
     * And replacing it with
     *   %result  = IMul32 %factor_a, %factor_b
     *
     * This optimization has been proven safe by LLVM and MSVC.
     */
    IR::Inst* const lhs_shl{inst.Arg(0).TryInstRecursive()};
    IR::Inst* const rhs_mul{inst.Arg(1).TryInstRecursive()};
    if (!lhs_shl || !rhs_mul) {
        return false;
    }
    if (lhs_shl->GetOpcode() != IR::Opcode::ShiftLeftLogical32 ||
        lhs_shl->Arg(1) != IR::Value{16U}) {
        return false;
    }
    IR::Inst* const lhs_mul{lhs_shl->Arg(0).TryInstRecursive()};
    if (!lhs_mul) {
        return false;
    }
    if (lhs_mul->GetOpcode() != IR::Opcode::IMul32 || rhs_mul->GetOpcode() != IR::Opcode::IMul32) {
        return false;
    }
    const IR::U32 factor_b{lhs_mul->Arg(1)};
    if (factor_b.Resolve() != rhs_mul->Arg(1).Resolve()) {
        return false;
    }
    IR::Inst* const lhs_bfe{lhs_mul->Arg(0).TryInstRecursive()};
    IR::Inst* const rhs_bfe{rhs_mul->Arg(0).TryInstRecursive()};
    if (!lhs_bfe || !rhs_bfe) {
        return false;
    }
    if (lhs_bfe->GetOpcode() != IR::Opcode::BitFieldUExtract) {
        return false;
    }
    if (rhs_bfe->GetOpcode() != IR::Opcode::BitFieldUExtract) {
        return false;
    }
    if (lhs_bfe->Arg(1) != IR::Value{16U} || lhs_bfe->Arg(2) != IR::Value{16U}) {
        return false;
    }
    if (rhs_bfe->Arg(1) != IR::Value{0U} || rhs_bfe->Arg(2) != IR::Value{16U}) {
        return false;
    }
    const IR::U32 factor_a{lhs_bfe->Arg(0)};
    if (factor_a.Resolve() != rhs_bfe->Arg(0).Resolve()) {
        return false;
    }
    IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
    inst.ReplaceUsesWith(ir.IMul(factor_a, factor_b));
    return true;
}

template <typename T>
void FoldAdd(IR::Block& block, IR::Inst& inst) {
    if (inst.HasAssociatedPseudoOperation()) {
        return;
    }
    if (!FoldCommutative<T>(inst, [](T a, T b) { return a + b; })) {
        return;
    }
    const IR::Value rhs{inst.Arg(1)};
    if (rhs.IsImmediate() && Arg<T>(rhs) == 0) {
        inst.ReplaceUsesWith(inst.Arg(0));
        return;
    }
    if constexpr (std::is_same_v<T, u32>) {
        if (FoldXmadMultiply(block, inst)) {
            return;
        }
        if (FoldXmadMultiplyAdd(block, inst)) {
            return;
        }
    }
}

void FoldISub32(IR::Inst& inst) {
    if (FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a - b; })) {
        return;
    }
    if (inst.Arg(0).IsImmediate() || inst.Arg(1).IsImmediate()) {
        return;
    }
    // ISub32 is generally used to subtract two constant buffers, compare and replace this with
    // zero if they equal.
    const auto equal_cbuf{[](IR::Inst* a, IR::Inst* b) {
        return a->GetOpcode() == IR::Opcode::GetCbufU32 &&
               b->GetOpcode() == IR::Opcode::GetCbufU32 && a->Arg(0) == b->Arg(0) &&
               a->Arg(1) == b->Arg(1);
    }};
    IR::Inst* op_a{inst.Arg(0).InstRecursive()};
    IR::Inst* op_b{inst.Arg(1).InstRecursive()};
    if (equal_cbuf(op_a, op_b)) {
        inst.ReplaceUsesWith(IR::Value{u32{0}});
        return;
    }
    // It's also possible a value is being added to a cbuf and then subtracted
    if (op_b->GetOpcode() == IR::Opcode::IAdd32) {
        // Canonicalize local variables to simplify the following logic
        std::swap(op_a, op_b);
    }
    if (op_b->GetOpcode() != IR::Opcode::GetCbufU32) {
        return;
    }
    IR::Inst* const inst_cbuf{op_b};
    if (op_a->GetOpcode() != IR::Opcode::IAdd32) {
        return;
    }
    IR::Value add_op_a{op_a->Arg(0)};
    IR::Value add_op_b{op_a->Arg(1)};
    if (add_op_b.IsImmediate()) {
        // Canonicalize
        std::swap(add_op_a, add_op_b);
    }
    if (add_op_b.IsImmediate()) {
        return;
    }
    IR::Inst* const add_cbuf{add_op_b.InstRecursive()};
    if (equal_cbuf(add_cbuf, inst_cbuf)) {
        inst.ReplaceUsesWith(add_op_a);
    }
}

void FoldSelect(IR::Inst& inst) {
    const IR::Value cond{inst.Arg(0)};
    if (cond.IsImmediate()) {
        inst.ReplaceUsesWith(cond.U1() ? inst.Arg(1) : inst.Arg(2));
    }
}

void FoldFPAdd32(IR::Inst& inst) {
    if (FoldWhenAllImmediates(inst, [](f32 a, f32 b) { return a + b; })) {
        return;
    }
    const IR::Value lhs_value{inst.Arg(0)};
    const IR::Value rhs_value{inst.Arg(1)};
    const auto check_neutral = [](const IR::Value& one_operand) {
        return one_operand.IsImmediate() && std::abs(one_operand.F32()) == 0.0f;
    };
    if (check_neutral(lhs_value)) {
        inst.ReplaceUsesWith(rhs_value);
    }
    if (check_neutral(rhs_value)) {
        inst.ReplaceUsesWith(lhs_value);
    }
}

bool FoldDerivativeYFromCorrection(IR::Inst& inst) {
    const IR::Value lhs_value{inst.Arg(0)};
    const IR::Value rhs_value{inst.Arg(1)};
    IR::Inst* const lhs_op{lhs_value.InstRecursive()};
    IR::Inst* const rhs_op{rhs_value.InstRecursive()};
    if (lhs_op->GetOpcode() == IR::Opcode::YDirection) {
        if (rhs_op->GetOpcode() != IR::Opcode::DPdyFine) {
            return false;
        }
        inst.ReplaceUsesWith(rhs_value);
        return true;
    }
    if (rhs_op->GetOpcode() != IR::Opcode::YDirection) {
        return false;
    }
    if (lhs_op->GetOpcode() != IR::Opcode::DPdyFine) {
        return false;
    }
    inst.ReplaceUsesWith(lhs_value);
    return true;
}

void FoldFPMul32(IR::Inst& inst) {
    if (FoldWhenAllImmediates(inst, [](f32 a, f32 b) { return a * b; })) {
        return;
    }
    const auto control{inst.Flags<IR::FpControl>()};
    if (control.no_contraction) {
        return;
    }
    // Fold interpolation operations
    const IR::Value lhs_value{inst.Arg(0)};
    const IR::Value rhs_value{inst.Arg(1)};
    if (lhs_value.IsImmediate() || rhs_value.IsImmediate()) {
        return;
    }
    if (FoldDerivativeYFromCorrection(inst)) {
        return;
    }
    IR::Inst* const lhs_op{lhs_value.InstRecursive()};
    IR::Inst* const rhs_op{rhs_value.InstRecursive()};
    if (lhs_op->GetOpcode() != IR::Opcode::FPMul32 ||
        rhs_op->GetOpcode() != IR::Opcode::FPRecip32) {
        return;
    }
    const IR::Value recip_source{rhs_op->Arg(0)};
    const IR::Value lhs_mul_source{lhs_op->Arg(1).Resolve()};
    if (recip_source.IsImmediate() || lhs_mul_source.IsImmediate()) {
        return;
    }
    IR::Inst* const attr_a{recip_source.InstRecursive()};
    IR::Inst* const attr_b{lhs_mul_source.InstRecursive()};
    if (attr_a->GetOpcode() != IR::Opcode::GetAttribute ||
        attr_b->GetOpcode() != IR::Opcode::GetAttribute) {
        return;
    }
    if (attr_a->Arg(0).Attribute() == attr_b->Arg(0).Attribute()) {
        inst.ReplaceUsesWith(lhs_op->Arg(0));
    }
}

void FoldLogicalAnd(IR::Inst& inst) {
    if (!FoldCommutative<bool>(inst, [](bool a, bool b) { return a && b; })) {
        return;
    }
    const IR::Value rhs{inst.Arg(1)};
    if (rhs.IsImmediate()) {
        if (rhs.U1()) {
            inst.ReplaceUsesWith(inst.Arg(0));
        } else {
            inst.ReplaceUsesWith(IR::Value{false});
        }
    }
}

void FoldLogicalOr(IR::Inst& inst) {
    if (!FoldCommutative<bool>(inst, [](bool a, bool b) { return a || b; })) {
        return;
    }
    const IR::Value rhs{inst.Arg(1)};
    if (rhs.IsImmediate()) {
        if (rhs.U1()) {
            inst.ReplaceUsesWith(IR::Value{true});
        } else {
            inst.ReplaceUsesWith(inst.Arg(0));
        }
    }
}

void FoldLogicalNot(IR::Inst& inst) {
    const IR::U1 value{inst.Arg(0)};
    if (value.IsImmediate()) {
        inst.ReplaceUsesWith(IR::Value{!value.U1()});
        return;
    }
    IR::Inst* const arg{value.InstRecursive()};
    if (arg->GetOpcode() == IR::Opcode::LogicalNot) {
        inst.ReplaceUsesWith(arg->Arg(0));
    }
}

template <IR::Opcode op, typename Dest, typename Source>
void FoldBitCast(IR::Inst& inst, IR::Opcode reverse) {
    const IR::Value value{inst.Arg(0)};
    if (value.IsImmediate()) {
        inst.ReplaceUsesWith(IR::Value{Common::BitCast<Dest>(Arg<Source>(value))});
        return;
    }
    IR::Inst* const arg_inst{value.InstRecursive()};
    if (arg_inst->GetOpcode() == reverse) {
        inst.ReplaceUsesWith(arg_inst->Arg(0));
        return;
    }
    if constexpr (op == IR::Opcode::BitCastF32U32) {
        if (arg_inst->GetOpcode() == IR::Opcode::GetCbufU32) {
            // Replace the bitcast with a typed constant buffer read
            inst.ReplaceOpcode(IR::Opcode::GetCbufF32);
            inst.SetArg(0, arg_inst->Arg(0));
            inst.SetArg(1, arg_inst->Arg(1));
            return;
        }
    }
    if constexpr (op == IR::Opcode::BitCastU32F32) {
        // Workaround for new NVIDIA driver bug, where:
        // uint attr = ftou(itof(gl_InstanceID));
        // always returned 0.
        // We can instead manually optimize this and work around the driver bug:
        // uint attr = uint(gl_InstanceID);
        if (arg_inst->GetOpcode() == IR::Opcode::GetAttribute) {
            const IR::Attribute attr{arg_inst->Arg(0).Attribute()};
            switch (attr) {
            case IR::Attribute::PrimitiveId:
            case IR::Attribute::InstanceId:
            case IR::Attribute::VertexId:
            case IR::Attribute::BaseVertex:
            case IR::Attribute::BaseInstance:
            case IR::Attribute::DrawID:
                break;
            default:
                return;
            }
            // Replace the bitcasts with an integer attribute get
            inst.ReplaceOpcode(IR::Opcode::GetAttributeU32);
            inst.SetArg(0, arg_inst->Arg(0));
            inst.SetArg(1, arg_inst->Arg(1));
            return;
        }
    }
}

void FoldInverseFunc(IR::Inst& inst, IR::Opcode reverse) {
    const IR::Value value{inst.Arg(0)};
    if (value.IsImmediate()) {
        return;
    }
    IR::Inst* const arg_inst{value.InstRecursive()};
    if (arg_inst->GetOpcode() == reverse) {
        inst.ReplaceUsesWith(arg_inst->Arg(0));
        return;
    }
}

template <typename Func, size_t... I>
IR::Value EvalImmediates(const IR::Inst& inst, Func&& func, std::index_sequence<I...>) {
    using Traits = LambdaTraits<decltype(func)>;
    return IR::Value{func(Arg<typename Traits::template ArgType<I>>(inst.Arg(I))...)};
}

std::optional<IR::Value> FoldCompositeExtractImpl(IR::Value inst_value, IR::Opcode insert,
                                                  IR::Opcode construct, u32 first_index) {
    IR::Inst* const inst{inst_value.InstRecursive()};
    if (inst->GetOpcode() == construct) {
        return inst->Arg(first_index);
    }
    if (inst->GetOpcode() != insert) {
        return std::nullopt;
    }
    IR::Value value_index{inst->Arg(2)};
    if (!value_index.IsImmediate()) {
        return std::nullopt;
    }
    const u32 second_index{value_index.U32()};
    if (first_index != second_index) {
        IR::Value value_composite{inst->Arg(0)};
        if (value_composite.IsImmediate()) {
            return std::nullopt;
        }
        return FoldCompositeExtractImpl(value_composite, insert, construct, first_index);
    }
    return inst->Arg(1);
}

void FoldCompositeExtract(IR::Inst& inst, IR::Opcode construct, IR::Opcode insert) {
    const IR::Value value_1{inst.Arg(0)};
    const IR::Value value_2{inst.Arg(1)};
    if (value_1.IsImmediate()) {
        return;
    }
    if (!value_2.IsImmediate()) {
        return;
    }
    const u32 first_index{value_2.U32()};
    const std::optional result{FoldCompositeExtractImpl(value_1, insert, construct, first_index)};
    if (!result) {
        return;
    }
    inst.ReplaceUsesWith(*result);
}

IR::Value GetThroughCast(IR::Value value, IR::Opcode expected_cast) {
    if (value.IsImmediate()) {
        return value;
    }
    IR::Inst* const inst{value.InstRecursive()};
    if (inst->GetOpcode() == expected_cast) {
        return inst->Arg(0).Resolve();
    }
    return value;
}

void FoldFSwizzleAdd(IR::Block& block, IR::Inst& inst) {
    const IR::Value swizzle{inst.Arg(2)};
    if (!swizzle.IsImmediate()) {
        return;
    }
    const IR::Value value_1{GetThroughCast(inst.Arg(0).Resolve(), IR::Opcode::BitCastF32U32)};
    const IR::Value value_2{GetThroughCast(inst.Arg(1).Resolve(), IR::Opcode::BitCastF32U32)};
    if (value_1.IsImmediate()) {
        return;
    }
    const u32 swizzle_value{swizzle.U32()};
    if (swizzle_value != 0x99 && swizzle_value != 0xA5) {
        return;
    }
    IR::Inst* const inst2{value_1.InstRecursive()};
    if (inst2->GetOpcode() != IR::Opcode::ShuffleButterfly) {
        return;
    }
    const IR::Value value_3{GetThroughCast(inst2->Arg(0).Resolve(), IR::Opcode::BitCastU32F32)};
    if (value_2 != value_3) {
        if (!value_2.IsImmediate() || !value_3.IsImmediate()) {
            return;
        }
        if (Common::BitCast<u32>(value_2.F32()) != value_3.U32()) {
            return;
        }
    }
    const IR::Value index{inst2->Arg(1)};
    const IR::Value clamp{inst2->Arg(2)};
    const IR::Value segmentation_mask{inst2->Arg(3)};
    if (!index.IsImmediate() || !clamp.IsImmediate() || !segmentation_mask.IsImmediate()) {
        return;
    }
    if (clamp.U32() != 3 || segmentation_mask.U32() != 28) {
        return;
    }
    if (swizzle_value == 0x99) {
        // DPdxFine
        if (index.U32() == 1) {
            IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
            inst.ReplaceUsesWith(ir.DPdxFine(IR::F32{inst.Arg(1)}));
        }
    } else if (swizzle_value == 0xA5) {
        // DPdyFine
        if (index.U32() == 2) {
            IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
            inst.ReplaceUsesWith(ir.DPdyFine(IR::F32{inst.Arg(1)}));
        }
    }
}

bool FindGradient3DDerivatives(std::array<IR::Value, 3>& results, IR::Value coord) {
    if (coord.IsImmediate()) {
        return false;
    }
    const auto check_through_shuffle = [](IR::Value input, IR::Value& result) {
        const IR::Value value_1{GetThroughCast(input.Resolve(), IR::Opcode::BitCastF32U32)};
        IR::Inst* const inst2{value_1.InstRecursive()};
        if (inst2->GetOpcode() != IR::Opcode::ShuffleIndex) {
            return false;
        }
        const IR::Value index{inst2->Arg(1).Resolve()};
        const IR::Value clamp{inst2->Arg(2).Resolve()};
        const IR::Value segmentation_mask{inst2->Arg(3).Resolve()};
        if (!index.IsImmediate() || !clamp.IsImmediate() || !segmentation_mask.IsImmediate()) {
            return false;
        }
        if (index.U32() != 3 && clamp.U32() != 3) {
            return false;
        }
        result = GetThroughCast(inst2->Arg(0).Resolve(), IR::Opcode::BitCastU32F32);
        return true;
    };
    IR::Inst* const inst = coord.InstRecursive();
    if (inst->GetOpcode() != IR::Opcode::FSwizzleAdd) {
        return false;
    }
    std::array<IR::Value, 3> temporary_values;
    IR::Value value_1 = inst->Arg(0).Resolve();
    IR::Value value_2 = inst->Arg(1).Resolve();
    IR::Value value_3 = inst->Arg(2).Resolve();
    std::array<u32, 4> swizzles_mask_a{};
    std::array<u32, 4> swizzles_mask_b{};
    const auto resolve_mask = [](std::array<u32, 4>& mask_results, IR::Value mask) {
        u32 value = mask.U32();
        for (size_t i = 0; i < 4; i++) {
            mask_results[i] = (value >> (i * 2)) & 0x3;
        }
    };
    resolve_mask(swizzles_mask_a, value_3);
    size_t coordinate_index = 0;
    const auto resolve_pending = [&](IR::Value resolve_v) {
        IR::Inst* const inst_r = resolve_v.InstRecursive();
        if (inst_r->GetOpcode() != IR::Opcode::FSwizzleAdd) {
            return false;
        }
        if (!check_through_shuffle(inst_r->Arg(0).Resolve(), temporary_values[1])) {
            return false;
        }
        if (!check_through_shuffle(inst_r->Arg(1).Resolve(), temporary_values[2])) {
            return false;
        }
        resolve_mask(swizzles_mask_b, inst_r->Arg(2).Resolve());
        return true;
    };
    if (value_1.IsImmediate() || value_2.IsImmediate()) {
        return false;
    }
    bool should_continue = false;
    if (resolve_pending(value_1)) {
        should_continue = check_through_shuffle(value_2, temporary_values[0]);
        coordinate_index = 0;
    }
    if (resolve_pending(value_2)) {
        should_continue = check_through_shuffle(value_1, temporary_values[0]);
        coordinate_index = 2;
    }
    if (!should_continue) {
        return false;
    }
    // figure which is which
    size_t zero_mask_a = 0;
    size_t zero_mask_b = 0;
    for (size_t i = 0; i < 4; i++) {
        if (swizzles_mask_a[i] == 2 || swizzles_mask_b[i] == 2) {
            // last operand can be inversed, we cannot determine a result.
            return false;
        }
        zero_mask_a |= static_cast<size_t>(swizzles_mask_a[i] == 3 ? 1 : 0) << i;
        zero_mask_b |= static_cast<size_t>(swizzles_mask_b[i] == 3 ? 1 : 0) << i;
    }
    static constexpr size_t ddx_pattern = 0b1010;
    static constexpr size_t ddx_pattern_inv = ~ddx_pattern & 0b00001111;
    if (std::popcount(zero_mask_a) != 2) {
        return false;
    }
    if (std::popcount(zero_mask_b) != 2) {
        return false;
    }
    if (zero_mask_a == zero_mask_b) {
        return false;
    }
    results[0] = temporary_values[coordinate_index];

    if (coordinate_index == 0) {
        if (zero_mask_b == ddx_pattern || zero_mask_b == ddx_pattern_inv) {
            results[1] = temporary_values[1];
            results[2] = temporary_values[2];
            return true;
        }
        results[2] = temporary_values[1];
        results[1] = temporary_values[2];
    } else {
        const auto assign_result = [&results](IR::Value temporary_value, size_t mask) {
            if (mask == ddx_pattern || mask == ddx_pattern_inv) {
                results[1] = temporary_value;
                return;
            }
            results[2] = temporary_value;
        };
        assign_result(temporary_values[1], zero_mask_b);
        assign_result(temporary_values[0], zero_mask_a);
    }

    return true;
}

void ConvertDerivatives(std::array<IR::Value, 3>& results, IR::IREmitter& ir) {
    for (size_t i = 0; i < 3; i++) {
        if (results[i].Type() == IR::Type::U32) {
            results[i] = results[i].IsImmediate() ? ir.Imm32(Common::BitCast<f32>(results[i].U32()))
                                                  : ir.BitCast<IR::F32>(IR::U32(results[i]));
        }
    }
}

void FoldImageSampleImplicitLod(IR::Block& block, IR::Inst& inst) {
    IR::TextureInstInfo info = inst.Flags<IR::TextureInstInfo>();
    auto orig_opcode = inst.GetOpcode();
    if (info.ndv_is_active == 0) {
        return;
    }
    if (info.type != TextureType::Color3D) {
        return;
    }
    const IR::Value handle{inst.Arg(0)};
    const IR::Value coords{inst.Arg(1)};
    const IR::Value bias_lc{inst.Arg(2)};
    const IR::Value offset{inst.Arg(3)};
    if (!offset.IsImmediate()) {
        return;
    }
    IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
    IR::Inst* const inst2 = coords.InstRecursive();
    std::array<std::array<IR::Value, 3>, 3> results_matrix;
    for (size_t i = 0; i < 3; i++) {
        if (!FindGradient3DDerivatives(results_matrix[i], inst2->Arg(i).Resolve())) {
            return;
        }
        ConvertDerivatives(results_matrix[i], ir);
    }
    IR::F32 lod_clamp{};
    if (info.has_lod_clamp != 0) {
        if (!bias_lc.IsImmediate()) {
            lod_clamp = IR::F32{bias_lc.InstRecursive()->Arg(1).Resolve()};
        } else {
            lod_clamp = IR::F32{bias_lc};
        }
    }
    IR::Value new_coords =
        ir.CompositeConstruct(results_matrix[0][0], results_matrix[1][0], results_matrix[2][0]);
    IR::Value derivatives_1 = ir.CompositeConstruct(results_matrix[0][1], results_matrix[0][2],
                                                    results_matrix[1][1], results_matrix[1][2]);
    IR::Value derivatives_2 = ir.CompositeConstruct(results_matrix[2][1], results_matrix[2][2]);
    info.num_derivatives.Assign(3);
    IR::Value new_gradient_instruction =
        ir.ImageGradient(handle, new_coords, derivatives_1, derivatives_2, lod_clamp, info);
    IR::Inst* const new_inst = new_gradient_instruction.InstRecursive();
    if (orig_opcode == IR::Opcode::ImageSampleImplicitLod) {
        new_inst->ReplaceOpcode(IR::Opcode::ImageGradient);
    }
    inst.ReplaceUsesWith(new_gradient_instruction);
}

void FoldConstBuffer(Environment& env, IR::Block& block, IR::Inst& inst) {
    const IR::Value bank{inst.Arg(0)};
    const IR::Value offset{inst.Arg(1)};
    if (!bank.IsImmediate() || !offset.IsImmediate()) {
        return;
    }
    const auto bank_value = bank.U32();
    const auto offset_value = offset.U32();
    auto replacement = env.GetReplaceConstBuffer(bank_value, offset_value);
    if (!replacement) {
        return;
    }
    const auto new_attribute = [replacement]() {
        switch (*replacement) {
        case ReplaceConstant::BaseInstance:
            return IR::Attribute::BaseInstance;
        case ReplaceConstant::BaseVertex:
            return IR::Attribute::BaseVertex;
        case ReplaceConstant::DrawID:
            return IR::Attribute::DrawID;
        default:
            throw NotImplementedException("Not implemented replacement variable {}", *replacement);
        }
    }();
    IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
    if (inst.GetOpcode() == IR::Opcode::GetCbufU32) {
        inst.ReplaceUsesWith(ir.GetAttributeU32(new_attribute));
    } else {
        inst.ReplaceUsesWith(ir.GetAttribute(new_attribute));
    }
}

void FoldDriverConstBuffer(Environment& env, IR::Block& block, IR::Inst& inst, u32 which_bank,
                           u32 offset_start = 0, u32 offset_end = std::numeric_limits<u16>::max()) {
    const IR::Value bank{inst.Arg(0)};
    const IR::Value offset{inst.Arg(1)};
    if (!bank.IsImmediate() || !offset.IsImmediate()) {
        return;
    }
    const auto bank_value = bank.U32();
    if (bank_value != which_bank) {
        return;
    }
    const auto offset_value = offset.U32();
    if (offset_value < offset_start || offset_value >= offset_end) {
        return;
    }
    IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
    if (inst.GetOpcode() == IR::Opcode::GetCbufU32) {
        inst.ReplaceUsesWith(IR::Value{env.ReadCbufValue(bank_value, offset_value)});
    } else {
        inst.ReplaceUsesWith(
            IR::Value{Common::BitCast<f32>(env.ReadCbufValue(bank_value, offset_value))});
    }
}

void ConstantPropagation(Environment& env, IR::Block& block, IR::Inst& inst) {
    switch (inst.GetOpcode()) {
    case IR::Opcode::GetRegister:
        return FoldGetRegister(inst);
    case IR::Opcode::GetPred:
        return FoldGetPred(inst);
    case IR::Opcode::IAdd32:
        return FoldAdd<u32>(block, inst);
    case IR::Opcode::ISub32:
        return FoldISub32(inst);
    case IR::Opcode::IMul32:
        FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a * b; });
        return;
    case IR::Opcode::ShiftRightArithmetic32:
        FoldWhenAllImmediates(inst, [](s32 a, s32 b) { return static_cast<u32>(a >> b); });
        return;
    case IR::Opcode::BitCastF32U32:
        return FoldBitCast<IR::Opcode::BitCastF32U32, f32, u32>(inst, IR::Opcode::BitCastU32F32);
    case IR::Opcode::BitCastU32F32:
        return FoldBitCast<IR::Opcode::BitCastU32F32, u32, f32>(inst, IR::Opcode::BitCastF32U32);
    case IR::Opcode::IAdd64:
        return FoldAdd<u64>(block, inst);
    case IR::Opcode::PackHalf2x16:
        return FoldInverseFunc(inst, IR::Opcode::UnpackHalf2x16);
    case IR::Opcode::UnpackHalf2x16:
        return FoldInverseFunc(inst, IR::Opcode::PackHalf2x16);
    case IR::Opcode::PackFloat2x16:
        return FoldInverseFunc(inst, IR::Opcode::UnpackFloat2x16);
    case IR::Opcode::UnpackFloat2x16:
        return FoldInverseFunc(inst, IR::Opcode::PackFloat2x16);
    case IR::Opcode::SelectU1:
    case IR::Opcode::SelectU8:
    case IR::Opcode::SelectU16:
    case IR::Opcode::SelectU32:
    case IR::Opcode::SelectU64:
    case IR::Opcode::SelectF16:
    case IR::Opcode::SelectF32:
    case IR::Opcode::SelectF64:
        return FoldSelect(inst);
    case IR::Opcode::FPNeg32:
        FoldWhenAllImmediates(inst, [](f32 a) { return -a; });
        return;
    case IR::Opcode::FPAdd32:
        FoldFPAdd32(inst);
        return;
    case IR::Opcode::FPMul32:
        return FoldFPMul32(inst);
    case IR::Opcode::LogicalAnd:
        return FoldLogicalAnd(inst);
    case IR::Opcode::LogicalOr:
        return FoldLogicalOr(inst);
    case IR::Opcode::LogicalNot:
        return FoldLogicalNot(inst);
    case IR::Opcode::SLessThan:
        FoldWhenAllImmediates(inst, [](s32 a, s32 b) { return a < b; });
        return;
    case IR::Opcode::ULessThan:
        FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a < b; });
        return;
    case IR::Opcode::SLessThanEqual:
        FoldWhenAllImmediates(inst, [](s32 a, s32 b) { return a <= b; });
        return;
    case IR::Opcode::ULessThanEqual:
        FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a <= b; });
        return;
    case IR::Opcode::SGreaterThan:
        FoldWhenAllImmediates(inst, [](s32 a, s32 b) { return a > b; });
        return;
    case IR::Opcode::UGreaterThan:
        FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a > b; });
        return;
    case IR::Opcode::SGreaterThanEqual:
        FoldWhenAllImmediates(inst, [](s32 a, s32 b) { return a >= b; });
        return;
    case IR::Opcode::UGreaterThanEqual:
        FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a >= b; });
        return;
    case IR::Opcode::IEqual:
        FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a == b; });
        return;
    case IR::Opcode::INotEqual:
        FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a != b; });
        return;
    case IR::Opcode::BitwiseAnd32:
        FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a & b; });
        return;
    case IR::Opcode::BitwiseOr32:
        FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a | b; });
        return;
    case IR::Opcode::BitwiseXor32:
        FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a ^ b; });
        return;
    case IR::Opcode::BitFieldUExtract:
        FoldWhenAllImmediates(inst, [](u32 base, u32 shift, u32 count) {
            if (static_cast<size_t>(shift) + static_cast<size_t>(count) > 32) {
                throw LogicError("Undefined result in {}({}, {}, {})", IR::Opcode::BitFieldUExtract,
                                 base, shift, count);
            }
            return (base >> shift) & ((1U << count) - 1);
        });
        return;
    case IR::Opcode::BitFieldSExtract:
        FoldWhenAllImmediates(inst, [](s32 base, u32 shift, u32 count) {
            const size_t back_shift{static_cast<size_t>(shift) + static_cast<size_t>(count)};
            const size_t left_shift{32 - back_shift};
            const size_t right_shift{static_cast<size_t>(32 - count)};
            if (back_shift > 32 || left_shift >= 32 || right_shift >= 32) {
                throw LogicError("Undefined result in {}({}, {}, {})", IR::Opcode::BitFieldSExtract,
                                 base, shift, count);
            }
            return static_cast<u32>((base << left_shift) >> right_shift);
        });
        return;
    case IR::Opcode::BitFieldInsert:
        FoldWhenAllImmediates(inst, [](u32 base, u32 insert, u32 offset, u32 bits) {
            if (bits >= 32 || offset >= 32) {
                throw LogicError("Undefined result in {}({}, {}, {}, {})",
                                 IR::Opcode::BitFieldInsert, base, insert, offset, bits);
            }
            return (base & ~(~(~0u << bits) << offset)) | (insert << offset);
        });
        return;
    case IR::Opcode::CompositeExtractU32x2:
        return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructU32x2,
                                    IR::Opcode::CompositeInsertU32x2);
    case IR::Opcode::CompositeExtractU32x3:
        return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructU32x3,
                                    IR::Opcode::CompositeInsertU32x3);
    case IR::Opcode::CompositeExtractU32x4:
        return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructU32x4,
                                    IR::Opcode::CompositeInsertU32x4);
    case IR::Opcode::CompositeExtractF32x2:
        return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF32x2,
                                    IR::Opcode::CompositeInsertF32x2);
    case IR::Opcode::CompositeExtractF32x3:
        return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF32x3,
                                    IR::Opcode::CompositeInsertF32x3);
    case IR::Opcode::CompositeExtractF32x4:
        return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF32x4,
                                    IR::Opcode::CompositeInsertF32x4);
    case IR::Opcode::CompositeExtractF16x2:
        return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF16x2,
                                    IR::Opcode::CompositeInsertF16x2);
    case IR::Opcode::CompositeExtractF16x3:
        return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF16x3,
                                    IR::Opcode::CompositeInsertF16x3);
    case IR::Opcode::CompositeExtractF16x4:
        return FoldCompositeExtract(inst, IR::Opcode::CompositeConstructF16x4,
                                    IR::Opcode::CompositeInsertF16x4);
    case IR::Opcode::FSwizzleAdd:
        return FoldFSwizzleAdd(block, inst);
    case IR::Opcode::GetCbufF32:
    case IR::Opcode::GetCbufU32:
        if (env.HasHLEMacroState()) {
            FoldConstBuffer(env, block, inst);
        }
        if (env.IsProprietaryDriver()) {
            FoldDriverConstBuffer(env, block, inst, 1);
        }
        break;
    case IR::Opcode::BindlessImageSampleImplicitLod:
    case IR::Opcode::BoundImageSampleImplicitLod:
    case IR::Opcode::ImageSampleImplicitLod:
        FoldImageSampleImplicitLod(block, inst);
        break;
    default:
        break;
    }
}

} // Anonymous namespace

void ConstantPropagationPass(Environment& env, IR::Program& program) {
    const auto end{program.post_order_blocks.rend()};
    for (auto it = program.post_order_blocks.rbegin(); it != end; ++it) {
        IR::Block* const block{*it};
        for (IR::Inst& inst : block->Instructions()) {
            ConstantPropagation(env, *block, inst);
        }
    }
}

} // namespace Shader::Optimization

repo_name: litucks/torzu

license: mit


code:
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later

#include "shader_recompiler/frontend/ir/basic_block.h"
#include "shader_recompiler/frontend/ir/value.h"
#include "shader_recompiler/ir_opt/passes.h"

namespace Shader::Optimization {

void DeadCodeEliminationPass(IR::Program& program) {
    // We iterate over the instructions in reverse order.
    // This is because removing an instruction reduces the number of uses for earlier instructions.
    for (IR::Block* const block : program.post_order_blocks) {
        auto it{block->end()};
        while (it != block->begin()) {
            --it;
            if (!it->HasUses() && !it->MayHaveSideEffects()) {
                it->Invalidate();
                it = block->Instructions().erase(it);
            }
        }
    }
}

} // namespace Shader::Optimization


code:
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later

#include "shader_recompiler/frontend/ir/ir_emitter.h"
#include "shader_recompiler/ir_opt/passes.h"

namespace Shader::Optimization {

void VertexATransformPass(IR::Program& program) {
    for (IR::Block* const block : program.blocks) {
        for (IR::Inst& inst : block->Instructions()) {
            if (inst.GetOpcode() == IR::Opcode::Epilogue) {
                return inst.Invalidate();
            }
        }
    }
}

void VertexBTransformPass(IR::Program& program) {
    for (IR::Block* const block : program.blocks) {
        for (IR::Inst& inst : block->Instructions()) {
            if (inst.GetOpcode() == IR::Opcode::Prologue) {
                return inst.Invalidate();
            }
        }
    }
}

} // namespace Shader::Optimization


code:
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later

#include <optional>

#include <boost/container/flat_set.hpp>
#include <boost/container/small_vector.hpp>

#include "common/alignment.h"
#include "shader_recompiler/frontend/ir/basic_block.h"
#include "shader_recompiler/frontend/ir/breadth_first_search.h"
#include "shader_recompiler/frontend/ir/ir_emitter.h"
#include "shader_recompiler/frontend/ir/value.h"
#include "shader_recompiler/host_translate_info.h"
#include "shader_recompiler/ir_opt/passes.h"

namespace Shader::Optimization {
namespace {
/// Address in constant buffers to the storage buffer descriptor
struct StorageBufferAddr {
    auto operator<=>(const StorageBufferAddr&) const noexcept = default;

    u32 index;
    u32 offset;
};

/// Block iterator to a global memory instruction and the storage buffer it uses
struct StorageInst {
    StorageBufferAddr storage_buffer;
    IR::Inst* inst;
    IR::Block* block;
};

/// Bias towards a certain range of constant buffers when looking for storage buffers
struct Bias {
    u32 index;
    u32 offset_begin;
    u32 offset_end;
    u32 alignment;
};

using boost::container::flat_set;
using boost::container::small_vector;
using StorageBufferSet =
    flat_set<StorageBufferAddr, std::less<StorageBufferAddr>, small_vector<StorageBufferAddr, 16>>;
using StorageInstVector = small_vector<StorageInst, 24>;
using StorageWritesSet =
    flat_set<StorageBufferAddr, std::less<StorageBufferAddr>, small_vector<StorageBufferAddr, 16>>;

struct StorageInfo {
    StorageBufferSet set;
    StorageInstVector to_replace;
    StorageWritesSet writes;
};

/// Returns true when the instruction is a global memory instruction
bool IsGlobalMemory(const IR::Inst& inst) {
    switch (inst.GetOpcode()) {
    case IR::Opcode::LoadGlobalS8:
    case IR::Opcode::LoadGlobalU8:
    case IR::Opcode::LoadGlobalS16:
    case IR::Opcode::LoadGlobalU16:
    case IR::Opcode::LoadGlobal32:
    case IR::Opcode::LoadGlobal64:
    case IR::Opcode::LoadGlobal128:
    case IR::Opcode::WriteGlobalS8:
    case IR::Opcode::WriteGlobalU8:
    case IR::Opcode::WriteGlobalS16:
    case IR::Opcode::WriteGlobalU16:
    case IR::Opcode::WriteGlobal32:
    case IR::Opcode::WriteGlobal64:
    case IR::Opcode::WriteGlobal128:
    case IR::Opcode::GlobalAtomicIAdd32:
    case IR::Opcode::GlobalAtomicSMin32:
    case IR::Opcode::GlobalAtomicUMin32:
    case IR::Opcode::GlobalAtomicSMax32:
    case IR::Opcode::GlobalAtomicUMax32:
    case IR::Opcode::GlobalAtomicInc32:
    case IR::Opcode::GlobalAtomicDec32:
    case IR::Opcode::GlobalAtomicAnd32:
    case IR::Opcode::GlobalAtomicOr32:
    case IR::Opcode::GlobalAtomicXor32:
    case IR::Opcode::GlobalAtomicExchange32:
    case IR::Opcode::GlobalAtomicIAdd64:
    case IR::Opcode::GlobalAtomicSMin64:
    case IR::Opcode::GlobalAtomicUMin64:
    case IR::Opcode::GlobalAtomicSMax64:
    case IR::Opcode::GlobalAtomicUMax64:
    case IR::Opcode::GlobalAtomicAnd64:
    case IR::Opcode::GlobalAtomicOr64:
    case IR::Opcode::GlobalAtomicXor64:
    case IR::Opcode::GlobalAtomicExchange64:
    case IR::Opcode::GlobalAtomicIAdd32x2:
    case IR::Opcode::GlobalAtomicSMin32x2:
    case IR::Opcode::GlobalAtomicUMin32x2:
    case IR::Opcode::GlobalAtomicSMax32x2:
    case IR::Opcode::GlobalAtomicUMax32x2:
    case IR::Opcode::GlobalAtomicAnd32x2:
    case IR::Opcode::GlobalAtomicOr32x2:
    case IR::Opcode::GlobalAtomicXor32x2:
    case IR::Opcode::GlobalAtomicExchange32x2:
    case IR::Opcode::GlobalAtomicAddF32:
    case IR::Opcode::GlobalAtomicAddF16x2:
    case IR::Opcode::GlobalAtomicAddF32x2:
    case IR::Opcode::GlobalAtomicMinF16x2:
    case IR::Opcode::GlobalAtomicMinF32x2:
    case IR::Opcode::GlobalAtomicMaxF16x2:
    case IR::Opcode::GlobalAtomicMaxF32x2:
        return true;
    default:
        return false;
    }
}

/// Returns true when the instruction is a global memory instruction
bool IsGlobalMemoryWrite(const IR::Inst& inst) {
    switch (inst.GetOpcode()) {
    case IR::Opcode::WriteGlobalS8:
    case IR::Opcode::WriteGlobalU8:
    case IR::Opcode::WriteGlobalS16:
    case IR::Opcode::WriteGlobalU16:
    case IR::Opcode::WriteGlobal32:
    case IR::Opcode::WriteGlobal64:
    case IR::Opcode::WriteGlobal128:
    case IR::Opcode::GlobalAtomicIAdd32:
    case IR::Opcode::GlobalAtomicSMin32:
    case IR::Opcode::GlobalAtomicUMin32:
    case IR::Opcode::GlobalAtomicSMax32:
    case IR::Opcode::GlobalAtomicUMax32:
    case IR::Opcode::GlobalAtomicInc32:
    case IR::Opcode::GlobalAtomicDec32:
    case IR::Opcode::GlobalAtomicAnd32:
    case IR::Opcode::GlobalAtomicOr32:
    case IR::Opcode::GlobalAtomicXor32:
    case IR::Opcode::GlobalAtomicExchange32:
    case IR::Opcode::GlobalAtomicIAdd64:
    case IR::Opcode::GlobalAtomicSMin64:
    case IR::Opcode::GlobalAtomicUMin64:
    case IR::Opcode::GlobalAtomicSMax64:
    case IR::Opcode::GlobalAtomicUMax64:
    case IR::Opcode::GlobalAtomicAnd64:
    case IR::Opcode::GlobalAtomicOr64:
    case IR::Opcode::GlobalAtomicXor64:
    case IR::Opcode::GlobalAtomicExchange64:
    case IR::Opcode::GlobalAtomicIAdd32x2:
    case IR::Opcode::GlobalAtomicSMin32x2:
    case IR::Opcode::GlobalAtomicUMin32x2:
    case IR::Opcode::GlobalAtomicSMax32x2:
    case IR::Opcode::GlobalAtomicUMax32x2:
    case IR::Opcode::GlobalAtomicAnd32x2:
    case IR::Opcode::GlobalAtomicOr32x2:
    case IR::Opcode::GlobalAtomicXor32x2:
    case IR::Opcode::GlobalAtomicExchange32x2:
    case IR::Opcode::GlobalAtomicAddF32:
    case IR::Opcode::GlobalAtomicAddF16x2:
    case IR::Opcode::GlobalAtomicAddF32x2:
    case IR::Opcode::GlobalAtomicMinF16x2:
    case IR::Opcode::GlobalAtomicMinF32x2:
    case IR::Opcode::GlobalAtomicMaxF16x2:
    case IR::Opcode::GlobalAtomicMaxF32x2:
        return true;
    default:
        return false;
    }
}

/// Converts a global memory opcode to its storage buffer equivalent
IR::Opcode GlobalToStorage(IR::Opcode opcode) {
    switch (opcode) {
    case IR::Opcode::LoadGlobalS8:
        return IR::Opcode::LoadStorageS8;
    case IR::Opcode::LoadGlobalU8:
        return IR::Opcode::LoadStorageU8;
    case IR::Opcode::LoadGlobalS16:
        return IR::Opcode::LoadStorageS16;
    case IR::Opcode::LoadGlobalU16:
        return IR::Opcode::LoadStorageU16;
    case IR::Opcode::LoadGlobal32:
        return IR::Opcode::LoadStorage32;
    case IR::Opcode::LoadGlobal64:
        return IR::Opcode::LoadStorage64;
    case IR::Opcode::LoadGlobal128:
        return IR::Opcode::LoadStorage128;
    case IR::Opcode::WriteGlobalS8:
        return IR::Opcode::WriteStorageS8;
    case IR::Opcode::WriteGlobalU8:
        return IR::Opcode::WriteStorageU8;
    case IR::Opcode::WriteGlobalS16:
        return IR::Opcode::WriteStorageS16;
    case IR::Opcode::WriteGlobalU16:
        return IR::Opcode::WriteStorageU16;
    case IR::Opcode::WriteGlobal32:
        return IR::Opcode::WriteStorage32;
    case IR::Opcode::WriteGlobal64:
        return IR::Opcode::WriteStorage64;
    case IR::Opcode::WriteGlobal128:
        return IR::Opcode::WriteStorage128;
    case IR::Opcode::GlobalAtomicIAdd32:
        return IR::Opcode::StorageAtomicIAdd32;
    case IR::Opcode::GlobalAtomicSMin32:
        return IR::Opcode::StorageAtomicSMin32;
    case IR::Opcode::GlobalAtomicUMin32:
        return IR::Opcode::StorageAtomicUMin32;
    case IR::Opcode::GlobalAtomicSMax32:
        return IR::Opcode::StorageAtomicSMax32;
    case IR::Opcode::GlobalAtomicUMax32:
        return IR::Opcode::StorageAtomicUMax32;
    case IR::Opcode::GlobalAtomicInc32:
        return IR::Opcode::StorageAtomicInc32;
    case IR::Opcode::GlobalAtomicDec32:
        return IR::Opcode::StorageAtomicDec32;
    case IR::Opcode::GlobalAtomicAnd32:
        return IR::Opcode::StorageAtomicAnd32;
    case IR::Opcode::GlobalAtomicOr32:
        return IR::Opcode::StorageAtomicOr32;
    case IR::Opcode::GlobalAtomicXor32:
        return IR::Opcode::StorageAtomicXor32;
    case IR::Opcode::GlobalAtomicExchange32:
        return IR::Opcode::StorageAtomicExchange32;
    case IR::Opcode::GlobalAtomicIAdd64:
        return IR::Opcode::StorageAtomicIAdd64;
    case IR::Opcode::GlobalAtomicSMin64:
        return IR::Opcode::StorageAtomicSMin64;
    case IR::Opcode::GlobalAtomicUMin64:
        return IR::Opcode::StorageAtomicUMin64;
    case IR::Opcode::GlobalAtomicSMax64:
        return IR::Opcode::StorageAtomicSMax64;
    case IR::Opcode::GlobalAtomicUMax64:
        return IR::Opcode::StorageAtomicUMax64;
    case IR::Opcode::GlobalAtomicAnd64:
        return IR::Opcode::StorageAtomicAnd64;
    case IR::Opcode::GlobalAtomicOr64:
        return IR::Opcode::StorageAtomicOr64;
    case IR::Opcode::GlobalAtomicXor64:
        return IR::Opcode::StorageAtomicXor64;
    case IR::Opcode::GlobalAtomicExchange64:
        return IR::Opcode::StorageAtomicExchange64;
    case IR::Opcode::GlobalAtomicIAdd32x2:
        return IR::Opcode::StorageAtomicIAdd32x2;
    case IR::Opcode::GlobalAtomicSMin32x2:
        return IR::Opcode::StorageAtomicSMin32x2;
    case IR::Opcode::GlobalAtomicUMin32x2:
        return IR::Opcode::StorageAtomicUMin32x2;
    case IR::Opcode::GlobalAtomicSMax32x2:
        return IR::Opcode::StorageAtomicSMax32x2;
    case IR::Opcode::GlobalAtomicUMax32x2:
        return IR::Opcode::StorageAtomicUMax32x2;
    case IR::Opcode::GlobalAtomicAnd32x2:
        return IR::Opcode::StorageAtomicAnd32x2;
    case IR::Opcode::GlobalAtomicOr32x2:
        return IR::Opcode::StorageAtomicOr32x2;
    case IR::Opcode::GlobalAtomicXor32x2:
        return IR::Opcode::StorageAtomicXor32x2;
    case IR::Opcode::GlobalAtomicExchange32x2:
        return IR::Opcode::StorageAtomicExchange32x2;
    case IR::Opcode::GlobalAtomicAddF32:
        return IR::Opcode::StorageAtomicAddF32;
    case IR::Opcode::GlobalAtomicAddF16x2:
        return IR::Opcode::StorageAtomicAddF16x2;
    case IR::Opcode::GlobalAtomicMinF16x2:
        return IR::Opcode::StorageAtomicMinF16x2;
    case IR::Opcode::GlobalAtomicMaxF16x2:
        return IR::Opcode::StorageAtomicMaxF16x2;
    case IR::Opcode::GlobalAtomicAddF32x2:
        return IR::Opcode::StorageAtomicAddF32x2;
    case IR::Opcode::GlobalAtomicMinF32x2:
        return IR::Opcode::StorageAtomicMinF32x2;
    case IR::Opcode::GlobalAtomicMaxF32x2:
        return IR::Opcode::StorageAtomicMaxF32x2;
    default:
        throw InvalidArgument("Invalid global memory opcode {}", opcode);
    }
}

/// Returns true when a storage buffer address satisfies a bias
bool MeetsBias(const StorageBufferAddr& storage_buffer, const Bias& bias) noexcept {
    return storage_buffer.index == bias.index && storage_buffer.offset >= bias.offset_begin &&
           storage_buffer.offset < bias.offset_end;
}

struct LowAddrInfo {
    IR::U32 value;
    s32 imm_offset;
};

/// Tries to track the first 32-bits of a global memory instruction
std::optional<LowAddrInfo> TrackLowAddress(IR::Inst* inst) {
    // The first argument is the low level GPU pointer to the global memory instruction
    const IR::Value addr{inst->Arg(0)};
    if (addr.IsImmediate()) {
        // Not much we can do if it's an immediate
        return std::nullopt;
    }
    // This address is expected to either be a PackUint2x32, a IAdd64, or a CompositeConstructU32x2
    IR::Inst* addr_inst{addr.InstRecursive()};
    s32 imm_offset{0};
    if (addr_inst->GetOpcode() == IR::Opcode::IAdd64) {
        // If it's an IAdd64, get the immediate offset it is applying and grab the address
        // instruction. This expects for the instruction to be canonicalized having the address on
        // the first argument and the immediate offset on the second one.
        const IR::U64 imm_offset_value{addr_inst->Arg(1)};
        if (!imm_offset_value.IsImmediate()) {
            return std::nullopt;
        }
        imm_offset = static_cast<s32>(static_cast<s64>(imm_offset_value.U64()));
        const IR::U64 iadd_addr{addr_inst->Arg(0)};
        if (iadd_addr.IsImmediate()) {
            return std::nullopt;
        }
        addr_inst = iadd_addr.InstRecursive();
    }
    // With IAdd64 handled, now PackUint2x32 is expected
    if (addr_inst->GetOpcode() == IR::Opcode::PackUint2x32) {
        // PackUint2x32 is expected to be generated from a vector
        const IR::Value vector{addr_inst->Arg(0)};
        if (vector.IsImmediate()) {
            return std::nullopt;
        }
        addr_inst = vector.InstRecursive();
    }
    // The vector is expected to be a CompositeConstructU32x2
    if (addr_inst->GetOpcode() != IR::Opcode::CompositeConstructU32x2) {
        return std::nullopt;
    }
    // Grab the first argument from the CompositeConstructU32x2, this is the low address.
    return LowAddrInfo{
        .value{IR::U32{addr_inst->Arg(0)}},
        .imm_offset = imm_offset,
    };
}

/// Tries to track the storage buffer address used by a global memory instruction
std::optional<StorageBufferAddr> Track(const IR::Value& value, const Bias* bias) {
    const auto pred{[bias](const IR::Inst* inst) -> std::optional<StorageBufferAddr> {
        if (inst->GetOpcode() != IR::Opcode::GetCbufU32 &&
            inst->GetOpcode() != IR::Opcode::GetCbufU32x2) {
            return std::nullopt;
        }
        const IR::Value index{inst->Arg(0)};
        const IR::Value offset{inst->Arg(1)};
        if (!index.IsImmediate()) {
            // Definitely not a storage buffer if it's read from a
            // non-immediate index
            return std::nullopt;
        }
        if (!offset.IsImmediate()) {
            // TODO: Support SSBO arrays
            return std::nullopt;
        }
        const StorageBufferAddr storage_buffer{
            .index = index.U32(),
            .offset = offset.U32(),
        };
        const u32 alignment{bias ? bias->alignment : 8U};
        if (!Common::IsAligned(storage_buffer.offset, alignment)) {
            // The SSBO pointer has to be aligned
            return std::nullopt;
        }
        if (bias && !MeetsBias(storage_buffer, *bias)) {
            // We have to blacklist some addresses in case we wrongly
            // point to them
            return std::nullopt;
        }
        return storage_buffer;
    }};
    return BreadthFirstSearch(value, pred);
}

/// Collects the storage buffer used by a global memory instruction and the instruction itself
void CollectStorageBuffers(IR::Block& block, IR::Inst& inst, StorageInfo& info) {
    // NVN puts storage buffers in a specific range, we have to bias towards these addresses to
    // avoid getting false positives
    static constexpr Bias nvn_bias{
        .index = 0,
        .offset_begin = 0x110,
        .offset_end = 0x610,
        .alignment = 16,
    };
    // Track the low address of the instruction
    const std::optional<LowAddrInfo> low_addr_info{TrackLowAddress(&inst)};
    if (!low_addr_info) {
        // Failed to track the low address, use NVN fallbacks
        return;
    }
    // First try to find storage buffers in the NVN address
    const IR::U32 low_addr{low_addr_info->value};
    std::optional<StorageBufferAddr> storage_buffer{Track(low_addr, &nvn_bias)};
    if (!storage_buffer) {
        // If it fails, track without a bias
        storage_buffer = Track(low_addr, nullptr);
        if (!storage_buffer) {
            // If that also fails, use NVN fallbacks
            LOG_WARNING(Shader, "Storage buffer failed to track, using global memory fallbacks");
            return;
        }
        LOG_WARNING(Shader, "Storage buffer tracked without bias, index {} offset {}",
                    storage_buffer->index, storage_buffer->offset);
    }
    // Collect storage buffer and the instruction
    if (IsGlobalMemoryWrite(inst)) {
        info.writes.insert(*storage_buffer);
    }
    info.set.insert(*storage_buffer);
    info.to_replace.push_back(StorageInst{
        .storage_buffer{*storage_buffer},
        .inst = &inst,
        .block = &block,
    });
}

/// Returns the offset in indices (not bytes) for an equivalent storage instruction
IR::U32 StorageOffset(IR::Block& block, IR::Inst& inst, StorageBufferAddr buffer, u32 alignment) {
    IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
    IR::U32 offset;
    if (const std::optional<LowAddrInfo> low_addr{TrackLowAddress(&inst)}) {
        offset = low_addr->value;
        if (low_addr->imm_offset != 0) {
            offset = ir.IAdd(offset, ir.Imm32(low_addr->imm_offset));
        }
    } else {
        offset = ir.UConvert(32, IR::U64{inst.Arg(0)});
    }
    // Subtract the least significant 32 bits from the guest offset. The result is the storage
    // buffer offset in bytes.
    IR::U32 low_cbuf{ir.GetCbuf(ir.Imm32(buffer.index), ir.Imm32(buffer.offset))};

    // Align the offset base to match the host alignment requirements
    low_cbuf = ir.BitwiseAnd(low_cbuf, ir.Imm32(~(alignment - 1U)));
    return ir.ISub(offset, low_cbuf);
}

/// Replace a global memory load instruction with its storage buffer equivalent
void ReplaceLoad(IR::Block& block, IR::Inst& inst, const IR::U32& storage_index,
                 const IR::U32& offset) {
    const IR::Opcode new_opcode{GlobalToStorage(inst.GetOpcode())};
    const auto it{IR::Block::InstructionList::s_iterator_to(inst)};
    const IR::Value value{&*block.PrependNewInst(it, new_opcode, {storage_index, offset})};
    inst.ReplaceUsesWith(value);
}

/// Replace a global memory write instruction with its storage buffer equivalent
void ReplaceWrite(IR::Block& block, IR::Inst& inst, const IR::U32& storage_index,
                  const IR::U32& offset) {
    const IR::Opcode new_opcode{GlobalToStorage(inst.GetOpcode())};
    const auto it{IR::Block::InstructionList::s_iterator_to(inst)};
    block.PrependNewInst(it, new_opcode, {storage_index, offset, inst.Arg(1)});
    inst.Invalidate();
}

/// Replace an atomic operation on global memory instruction with its storage buffer equivalent
void ReplaceAtomic(IR::Block& block, IR::Inst& inst, const IR::U32& storage_index,
                   const IR::U32& offset) {
    const IR::Opcode new_opcode{GlobalToStorage(inst.GetOpcode())};
    const auto it{IR::Block::InstructionList::s_iterator_to(inst)};
    const IR::Value value{
        &*block.PrependNewInst(it, new_opcode, {storage_index, offset, inst.Arg(1)})};
    inst.ReplaceUsesWith(value);
}

/// Replace a global memory instruction with its storage buffer equivalent
void Replace(IR::Block& block, IR::Inst& inst, const IR::U32& storage_index,
             const IR::U32& offset) {
    switch (inst.GetOpcode()) {
    case IR::Opcode::LoadGlobalS8:
    case IR::Opcode::LoadGlobalU8:
    case IR::Opcode::LoadGlobalS16:
    case IR::Opcode::LoadGlobalU16:
    case IR::Opcode::LoadGlobal32:
    case IR::Opcode::LoadGlobal64:
    case IR::Opcode::LoadGlobal128:
        return ReplaceLoad(block, inst, storage_index, offset);
    case IR::Opcode::WriteGlobalS8:
    case IR::Opcode::WriteGlobalU8:
    case IR::Opcode::WriteGlobalS16:
    case IR::Opcode::WriteGlobalU16:
    case IR::Opcode::WriteGlobal32:
    case IR::Opcode::WriteGlobal64:
    case IR::Opcode::WriteGlobal128:
        return ReplaceWrite(block, inst, storage_index, offset);
    case IR::Opcode::GlobalAtomicIAdd32:
    case IR::Opcode::GlobalAtomicSMin32:
    case IR::Opcode::GlobalAtomicUMin32:
    case IR::Opcode::GlobalAtomicSMax32:
    case IR::Opcode::GlobalAtomicUMax32:
    case IR::Opcode::GlobalAtomicInc32:
    case IR::Opcode::GlobalAtomicDec32:
    case IR::Opcode::GlobalAtomicAnd32:
    case IR::Opcode::GlobalAtomicOr32:
    case IR::Opcode::GlobalAtomicXor32:
    case IR::Opcode::GlobalAtomicExchange32:
    case IR::Opcode::GlobalAtomicIAdd64:
    case IR::Opcode::GlobalAtomicSMin64:
    case IR::Opcode::GlobalAtomicUMin64:
    case IR::Opcode::GlobalAtomicSMax64:
    case IR::Opcode::GlobalAtomicUMax64:
    case IR::Opcode::GlobalAtomicAnd64:
    case IR::Opcode::GlobalAtomicOr64:
    case IR::Opcode::GlobalAtomicXor64:
    case IR::Opcode::GlobalAtomicExchange64:
    case IR::Opcode::GlobalAtomicIAdd32x2:
    case IR::Opcode::GlobalAtomicSMin32x2:
    case IR::Opcode::GlobalAtomicUMin32x2:
    case IR::Opcode::GlobalAtomicSMax32x2:
    case IR::Opcode::GlobalAtomicUMax32x2:
    case IR::Opcode::GlobalAtomicAnd32x2:
    case IR::Opcode::GlobalAtomicOr32x2:
    case IR::Opcode::GlobalAtomicXor32x2:
    case IR::Opcode::GlobalAtomicExchange32x2:
    case IR::Opcode::GlobalAtomicAddF32:
    case IR::Opcode::GlobalAtomicAddF16x2:
    case IR::Opcode::GlobalAtomicAddF32x2:
    case IR::Opcode::GlobalAtomicMinF16x2:
    case IR::Opcode::GlobalAtomicMinF32x2:
    case IR::Opcode::GlobalAtomicMaxF16x2:
    case IR::Opcode::GlobalAtomicMaxF32x2:
        return ReplaceAtomic(block, inst, storage_index, offset);
    default:
        throw InvalidArgument("Invalid global memory opcode {}", inst.GetOpcode());
    }
}
} // Anonymous namespace

void GlobalMemoryToStorageBufferPass(IR::Program& program, const HostTranslateInfo& host_info) {
    StorageInfo info;
    for (IR::Block* const block : program.post_order_blocks) {
        for (IR::Inst& inst : block->Instructions()) {
            if (!IsGlobalMemory(inst)) {
                continue;
            }
            CollectStorageBuffers(*block, inst, info);
        }
    }
    for (const StorageBufferAddr& storage_buffer : info.set) {
        program.info.storage_buffers_descriptors.push_back({
            .cbuf_index = storage_buffer.index,
            .cbuf_offset = storage_buffer.offset,
            .count = 1,
            .is_written = info.writes.contains(storage_buffer),
        });
    }
    for (const StorageInst& storage_inst : info.to_replace) {
        const StorageBufferAddr storage_buffer{storage_inst.storage_buffer};
        const auto it{info.set.find(storage_inst.storage_buffer)};
        const IR::U32 index{IR::Value{static_cast<u32>(info.set.index_of(it))}};
        IR::Block* const block{storage_inst.block};
        IR::Inst* const inst{storage_inst.inst};
        const IR::U32 offset{
            StorageOffset(*block, *inst, storage_buffer, host_info.min_ssbo_alignment)};
        Replace(*block, *inst, index, offset);
    }
}

template <typename Descriptors, typename Descriptor, typename Func>
static u32 Add(Descriptors& descriptors, const Descriptor& desc, Func&& pred) {
    // TODO: Handle arrays
    const auto it{std::ranges::find_if(descriptors, pred)};
    if (it != descriptors.end()) {
        return static_cast<u32>(std::distance(descriptors.begin(), it));
    }
    descriptors.push_back(desc);
    return static_cast<u32>(descriptors.size()) - 1;
}

void JoinStorageInfo(Info& base, Info& source) {
    auto& descriptors = base.storage_buffers_descriptors;
    for (auto& desc : source.storage_buffers_descriptors) {
        auto it{std::ranges::find_if(descriptors, [&desc](const auto& existing) {
            return desc.cbuf_index == existing.cbuf_index &&
                   desc.cbuf_offset == existing.cbuf_offset && desc.count == existing.count;
        })};
        if (it != descriptors.end()) {
            it->is_written |= desc.is_written;
            continue;
        }
        descriptors.push_back(desc);
    }
}

} // namespace Shader::Optimization


code:
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later

#include <vector>

#include "shader_recompiler/frontend/ir/basic_block.h"
#include "shader_recompiler/frontend/ir/value.h"
#include "shader_recompiler/ir_opt/passes.h"

namespace Shader::Optimization {

void IdentityRemovalPass(IR::Program& program) {
    std::vector<IR::Inst*> to_invalidate;
    for (IR::Block* const block : program.blocks) {
        for (auto inst = block->begin(); inst != block->end();) {
            const size_t num_args{inst->NumArgs()};
            for (size_t i = 0; i < num_args; ++i) {
                IR::Value arg;
                while ((arg = inst->Arg(i)).IsIdentity()) {
                    inst->SetArg(i, arg.Inst()->Arg(0));
                }
            }
            if (inst->GetOpcode() == IR::Opcode::Identity ||
                inst->GetOpcode() == IR::Opcode::Void) {
                to_invalidate.push_back(&*inst);
                inst = block->Instructions().erase(inst);
            } else {
                ++inst;
            }
        }
    }
    for (IR::Inst* const inst : to_invalidate) {
        inst->Invalidate();
    }
}

} // namespace Shader::Optimization


code:
// SPDX-FileCopyrightText: Copyright 2022 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later

#include <algorithm>
#include <bit>
#include <optional>

#include <boost/container/small_vector.hpp>

#include "shader_recompiler/environment.h"
#include "shader_recompiler/frontend/ir/basic_block.h"
#include "shader_recompiler/frontend/ir/breadth_first_search.h"
#include "shader_recompiler/frontend/ir/ir_emitter.h"
#include "shader_recompiler/host_translate_info.h"
#include "shader_recompiler/ir_opt/passes.h"
#include "shader_recompiler/shader_info.h"

namespace Shader::Optimization {

static IR::Attribute EmulatedLayerAttribute(VaryingState& stores) {
    for (u32 i = 0; i < 32; i++) {
        if (!stores.Generic(i)) {
            return IR::Attribute::Generic0X + (i * 4);
        }
    }
    return IR::Attribute::Layer;
}

static bool PermittedProgramStage(Stage stage) {
    switch (stage) {
    case Stage::VertexA:
    case Stage::VertexB:
    case Stage::TessellationControl:
    case Stage::TessellationEval:
        return true;
    default:
        return false;
    }
}

void LayerPass(IR::Program& program, const HostTranslateInfo& host_info) {
    if (host_info.support_viewport_index_layer || !PermittedProgramStage(program.stage)) {
        return;
    }

    const auto end{program.post_order_blocks.end()};
    const auto layer_attribute = EmulatedLayerAttribute(program.info.stores);
    bool requires_layer_emulation = false;

    for (auto block = program.post_order_blocks.begin(); block != end; ++block) {
        for (IR::Inst& inst : (*block)->Instructions()) {
            if (inst.GetOpcode() == IR::Opcode::SetAttribute &&
                inst.Arg(0).Attribute() == IR::Attribute::Layer) {
                requires_layer_emulation = true;
                inst.SetArg(0, IR::Value{layer_attribute});
            }
        }
    }

    if (requires_layer_emulation) {
        program.info.requires_layer_emulation = true;
        program.info.emulated_layer = layer_attribute;
        program.info.stores.Set(IR::Attribute::Layer, false);
        program.info.stores.Set(layer_attribute, true);
    }
}

} // namespace Shader::Optimization


code:
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later

#include "shader_recompiler/frontend/ir/value.h"
#include "shader_recompiler/ir_opt/passes.h"

namespace Shader::Optimization {
namespace {
IR::Opcode Replace(IR::Opcode op) {
    switch (op) {
    case IR::Opcode::FPAbs16:
        return IR::Opcode::FPAbs32;
    case IR::Opcode::FPAdd16:
        return IR::Opcode::FPAdd32;
    case IR::Opcode::FPCeil16:
        return IR::Opcode::FPCeil32;
    case IR::Opcode::FPFloor16:
        return IR::Opcode::FPFloor32;
    case IR::Opcode::FPFma16:
        return IR::Opcode::FPFma32;
    case IR::Opcode::FPMul16:
        return IR::Opcode::FPMul32;
    case IR::Opcode::FPNeg16:
        return IR::Opcode::FPNeg32;
    case IR::Opcode::FPRoundEven16:
        return IR::Opcode::FPRoundEven32;
    case IR::Opcode::FPSaturate16:
        return IR::Opcode::FPSaturate32;
    case IR::Opcode::FPClamp16:
        return IR::Opcode::FPClamp32;
    case IR::Opcode::FPTrunc16:
        return IR::Opcode::FPTrunc32;
    case IR::Opcode::CompositeConstructF16x2:
        return IR::Opcode::CompositeConstructF32x2;
    case IR::Opcode::CompositeConstructF16x3:
        return IR::Opcode::CompositeConstructF32x3;
    case IR::Opcode::CompositeConstructF16x4:
        return IR::Opcode::CompositeConstructF32x4;
    case IR::Opcode::CompositeExtractF16x2:
        return IR::Opcode::CompositeExtractF32x2;
    case IR::Opcode::CompositeExtractF16x3:
        return IR::Opcode::CompositeExtractF32x3;
    case IR::Opcode::CompositeExtractF16x4:
        return IR::Opcode::CompositeExtractF32x4;
    case IR::Opcode::CompositeInsertF16x2:
        return IR::Opcode::CompositeInsertF32x2;
    case IR::Opcode::CompositeInsertF16x3:
        return IR::Opcode::CompositeInsertF32x3;
    case IR::Opcode::CompositeInsertF16x4:
        return IR::Opcode::CompositeInsertF32x4;
    case IR::Opcode::FPOrdEqual16:
        return IR::Opcode::FPOrdEqual32;
    case IR::Opcode::FPUnordEqual16:
        return IR::Opcode::FPUnordEqual32;
    case IR::Opcode::FPOrdNotEqual16:
        return IR::Opcode::FPOrdNotEqual32;
    case IR::Opcode::FPUnordNotEqual16:
        return IR::Opcode::FPUnordNotEqual32;
    case IR::Opcode::FPOrdLessThan16:
        return IR::Opcode::FPOrdLessThan32;
    case IR::Opcode::FPUnordLessThan16:
        return IR::Opcode::FPUnordLessThan32;
    case IR::Opcode::FPOrdGreaterThan16:
        return IR::Opcode::FPOrdGreaterThan32;
    case IR::Opcode::FPUnordGreaterThan16:
        return IR::Opcode::FPUnordGreaterThan32;
    case IR::Opcode::FPOrdLessThanEqual16:
        return IR::Opcode::FPOrdLessThanEqual32;
    case IR::Opcode::FPUnordLessThanEqual16:
        return IR::Opcode::FPUnordLessThanEqual32;
    case IR::Opcode::FPOrdGreaterThanEqual16:
        return IR::Opcode::FPOrdGreaterThanEqual32;
    case IR::Opcode::FPUnordGreaterThanEqual16:
        return IR::Opcode::FPUnordGreaterThanEqual32;
    case IR::Opcode::FPIsNan16:
        return IR::Opcode::FPIsNan32;
    case IR::Opcode::ConvertS16F16:
        return IR::Opcode::ConvertS16F32;
    case IR::Opcode::ConvertS32F16:
        return IR::Opcode::ConvertS32F32;
    case IR::Opcode::ConvertS64F16:
        return IR::Opcode::ConvertS64F32;
    case IR::Opcode::ConvertU16F16:
        return IR::Opcode::ConvertU16F32;
    case IR::Opcode::ConvertU32F16:
        return IR::Opcode::ConvertU32F32;
    case IR::Opcode::ConvertU64F16:
        return IR::Opcode::ConvertU64F32;
    case IR::Opcode::PackFloat2x16:
        return IR::Opcode::PackHalf2x16;
    case IR::Opcode::UnpackFloat2x16:
        return IR::Opcode::UnpackHalf2x16;
    case IR::Opcode::ConvertF32F16:
        return IR::Opcode::Identity;
    case IR::Opcode::ConvertF16F32:
        return IR::Opcode::Identity;
    case IR::Opcode::ConvertF16S8:
        return IR::Opcode::ConvertF32S8;
    case IR::Opcode::ConvertF16S16:
        return IR::Opcode::ConvertF32S16;
    case IR::Opcode::ConvertF16S32:
        return IR::Opcode::ConvertF32S32;
    case IR::Opcode::ConvertF16S64:
        return IR::Opcode::ConvertF32S64;
    case IR::Opcode::ConvertF16U8:
        return IR::Opcode::ConvertF32U8;
    case IR::Opcode::ConvertF16U16:
        return IR::Opcode::ConvertF32U16;
    case IR::Opcode::ConvertF16U32:
        return IR::Opcode::ConvertF32U32;
    case IR::Opcode::ConvertF16U64:
        return IR::Opcode::ConvertF32U64;
    case IR::Opcode::GlobalAtomicAddF16x2:
        return IR::Opcode::GlobalAtomicAddF32x2;
    case IR::Opcode::StorageAtomicAddF16x2:
        return IR::Opcode::StorageAtomicAddF32x2;
    case IR::Opcode::GlobalAtomicMinF16x2:
        return IR::Opcode::GlobalAtomicMinF32x2;
    case IR::Opcode::StorageAtomicMinF16x2:
        return IR::Opcode::StorageAtomicMinF32x2;
    case IR::Opcode::GlobalAtomicMaxF16x2:
        return IR::Opcode::GlobalAtomicMaxF32x2;
    case IR::Opcode::StorageAtomicMaxF16x2:
        return IR::Opcode::StorageAtomicMaxF32x2;
    default:
        return op;
    }
}
} // Anonymous namespace

void LowerFp16ToFp32(IR::Program& program) {
    for (IR::Block* const block : program.blocks) {
        for (IR::Inst& inst : block->Instructions()) {
            inst.ReplaceOpcode(Replace(inst.GetOpcode()));
        }
    }
}

} // namespace Shader::Optimization


code:
// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later

#include "shader_recompiler/frontend/ir/ir_emitter.h"
#include "shader_recompiler/frontend/ir/opcodes.h"
#include "shader_recompiler/frontend/ir/value.h"
#include "shader_recompiler/ir_opt/passes.h"

namespace Shader::Optimization {
namespace {

constexpr s32 F64ToF32Exp = +1023 - 127;
constexpr s32 F32ToF64Exp = +127 - 1023;

IR::F32 PackedF64ToF32(IR::IREmitter& ir, const IR::Value& packed) {
    const IR::U32 lo{ir.CompositeExtract(packed, 0)};
    const IR::U32 hi{ir.CompositeExtract(packed, 1)};
    const IR::U32 sign{ir.BitFieldExtract(hi, ir.Imm32(31), ir.Imm32(1))};
    const IR::U32 exp{ir.BitFieldExtract(hi, ir.Imm32(20), ir.Imm32(11))};
    const IR::U32 mantissa_hi{ir.BitFieldExtract(hi, ir.Imm32(0), ir.Imm32(20))};
    const IR::U32 mantissa_lo{ir.BitFieldExtract(lo, ir.Imm32(29), ir.Imm32(3))};
    const IR::U32 mantissa{
        ir.BitwiseOr(ir.ShiftLeftLogical(mantissa_hi, ir.Imm32(3)), mantissa_lo)};
    const IR::U32 exp_if_subnorm{
        ir.Select(ir.IEqual(exp, ir.Imm32(0)), ir.Imm32(0), ir.IAdd(exp, ir.Imm32(F64ToF32Exp)))};
    const IR::U32 exp_if_infnan{
        ir.Select(ir.IEqual(exp, ir.Imm32(0x7ff)), ir.Imm32(0xff), exp_if_subnorm)};
    const IR::U32 result{
        ir.BitwiseOr(ir.ShiftLeftLogical(sign, ir.Imm32(31)),
                     ir.BitwiseOr(ir.ShiftLeftLogical(exp_if_infnan, ir.Imm32(23)), mantissa))};
    return ir.BitCast<IR::F32>(result);
}

IR::Value F32ToPackedF64(IR::IREmitter& ir, const IR::Value& raw) {
    const IR::U32 value{ir.BitCast<IR::U32>(IR::F32(raw))};
    const IR::U32 sign{ir.BitFieldExtract(value, ir.Imm32(31), ir.Imm32(1))};
    const IR::U32 exp{ir.BitFieldExtract(value, ir.Imm32(23), ir.Imm32(8))};
    const IR::U32 mantissa{ir.BitFieldExtract(value, ir.Imm32(0), ir.Imm32(23))};
    const IR::U32 mantissa_hi{ir.BitFieldExtract(mantissa, ir.Imm32(3), ir.Imm32(20))};
    const IR::U32 mantissa_lo{ir.BitFieldExtract(mantissa, ir.Imm32(0), ir.Imm32(3))};
    const IR::U32 exp_if_subnorm{
        ir.Select(ir.IEqual(exp, ir.Imm32(0)), ir.Imm32(0), ir.IAdd(exp, ir.Imm32(F32ToF64Exp)))};
    const IR::U32 exp_if_infnan{
        ir.Select(ir.IEqual(exp, ir.Imm32(0xff)), ir.Imm32(0x7ff), exp_if_subnorm)};
    const IR::U32 lo{ir.ShiftLeftLogical(mantissa_lo, ir.Imm32(29))};
    const IR::U32 hi{
        ir.BitwiseOr(ir.ShiftLeftLogical(sign, ir.Imm32(31)),
                     ir.BitwiseOr(ir.ShiftLeftLogical(exp_if_infnan, ir.Imm32(20)), mantissa_hi))};
    return ir.CompositeConstruct(lo, hi);
}

IR::Opcode Replace(IR::Opcode op) {
    switch (op) {
    case IR::Opcode::FPAbs64:
        return IR::Opcode::FPAbs32;
    case IR::Opcode::FPAdd64:
        return IR::Opcode::FPAdd32;
    case IR::Opcode::FPCeil64:
        return IR::Opcode::FPCeil32;
    case IR::Opcode::FPFloor64:
        return IR::Opcode::FPFloor32;
    case IR::Opcode::FPFma64:
        return IR::Opcode::FPFma32;
    case IR::Opcode::FPMul64:
        return IR::Opcode::FPMul32;
    case IR::Opcode::FPNeg64:
        return IR::Opcode::FPNeg32;
    case IR::Opcode::FPRoundEven64:
        return IR::Opcode::FPRoundEven32;
    case IR::Opcode::FPSaturate64:
        return IR::Opcode::FPSaturate32;
    case IR::Opcode::FPClamp64:
        return IR::Opcode::FPClamp32;
    case IR::Opcode::FPTrunc64:
        return IR::Opcode::FPTrunc32;
    case IR::Opcode::CompositeConstructF64x2:
        return IR::Opcode::CompositeConstructF32x2;
    case IR::Opcode::CompositeConstructF64x3:
        return IR::Opcode::CompositeConstructF32x3;
    case IR::Opcode::CompositeConstructF64x4:
        return IR::Opcode::CompositeConstructF32x4;
    case IR::Opcode::CompositeExtractF64x2:
        return IR::Opcode::CompositeExtractF32x2;
    case IR::Opcode::CompositeExtractF64x3:
        return IR::Opcode::CompositeExtractF32x3;
    case IR::Opcode::CompositeExtractF64x4:
        return IR::Opcode::CompositeExtractF32x4;
    case IR::Opcode::CompositeInsertF64x2:
        return IR::Opcode::CompositeInsertF32x2;
    case IR::Opcode::CompositeInsertF64x3:
        return IR::Opcode::CompositeInsertF32x3;
    case IR::Opcode::CompositeInsertF64x4:
        return IR::Opcode::CompositeInsertF32x4;
    case IR::Opcode::FPOrdEqual64:
        return IR::Opcode::FPOrdEqual32;
    case IR::Opcode::FPUnordEqual64:
        return IR::Opcode::FPUnordEqual32;
    case IR::Opcode::FPOrdNotEqual64:
        return IR::Opcode::FPOrdNotEqual32;
    case IR::Opcode::FPUnordNotEqual64:
        return IR::Opcode::FPUnordNotEqual32;
    case IR::Opcode::FPOrdLessThan64:
        return IR::Opcode::FPOrdLessThan32;
    case IR::Opcode::FPUnordLessThan64:
        return IR::Opcode::FPUnordLessThan32;
    case IR::Opcode::FPOrdGreaterThan64:
        return IR::Opcode::FPOrdGreaterThan32;
    case IR::Opcode::FPUnordGreaterThan64:
        return IR::Opcode::FPUnordGreaterThan32;
    case IR::Opcode::FPOrdLessThanEqual64:
        return IR::Opcode::FPOrdLessThanEqual32;
    case IR::Opcode::FPUnordLessThanEqual64:
        return IR::Opcode::FPUnordLessThanEqual32;
    case IR::Opcode::FPOrdGreaterThanEqual64:
        return IR::Opcode::FPOrdGreaterThanEqual32;
    case IR::Opcode::FPUnordGreaterThanEqual64:
        return IR::Opcode::FPUnordGreaterThanEqual32;
    case IR::Opcode::FPIsNan64:
        return IR::Opcode::FPIsNan32;
    case IR::Opcode::ConvertS16F64:
        return IR::Opcode::ConvertS16F32;
    case IR::Opcode::ConvertS32F64:
        return IR::Opcode::ConvertS32F32;
    case IR::Opcode::ConvertS64F64:
        return IR::Opcode::ConvertS64F32;
    case IR::Opcode::ConvertU16F64:
        return IR::Opcode::ConvertU16F32;
    case IR::Opcode::ConvertU32F64:
        return IR::Opcode::ConvertU32F32;
    case IR::Opcode::ConvertU64F64:
        return IR::Opcode::ConvertU64F32;
    case IR::Opcode::ConvertF32F64:
        return IR::Opcode::Identity;
    case IR::Opcode::ConvertF64F32:
        return IR::Opcode::Identity;
    case IR::Opcode::ConvertF64S8:
        return IR::Opcode::ConvertF32S8;
    case IR::Opcode::ConvertF64S16:
        return IR::Opcode::ConvertF32S16;
    case IR::Opcode::ConvertF64S32:
        return IR::Opcode::ConvertF32S32;
    case IR::Opcode::ConvertF64S64:
        return IR::Opcode::ConvertF32S64;
    case IR::Opcode::ConvertF64U8:
        return IR::Opcode::ConvertF32U8;
    case IR::Opcode::ConvertF64U16:
        return IR::Opcode::ConvertF32U16;
    case IR::Opcode::ConvertF64U32:
        return IR::Opcode::ConvertF32U32;
    case IR::Opcode::ConvertF64U64:
        return IR::Opcode::ConvertF32U64;
    default:
        return op;
    }
}

void Lower(IR::Block& block, IR::Inst& inst) {
    switch (inst.GetOpcode()) {
    case IR::Opcode::PackDouble2x32: {
        IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
        inst.ReplaceUsesWith(PackedF64ToF32(ir, inst.Arg(0)));
        break;
    }
    case IR::Opcode::UnpackDouble2x32: {
        IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
        inst.ReplaceUsesWith(F32ToPackedF64(ir, inst.Arg(0)));
        break;
    }
    default:
        inst.ReplaceOpcode(Replace(inst.GetOpcode()));
        break;
    }
}

} // Anonymous namespace

void LowerFp64ToFp32(IR::Program& program) {
    for (IR::Block* const block : program.blocks) {
        for (IR::Inst& inst : block->Instructions()) {
            Lower(*block, inst);
        }
    }
}

} // namespace Shader::Optimization


code:
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later

#include <utility>

#include "shader_recompiler/exception.h"
#include "shader_recompiler/frontend/ir/basic_block.h"
#include "shader_recompiler/frontend/ir/ir_emitter.h"
#include "shader_recompiler/frontend/ir/program.h"
#include "shader_recompiler/frontend/ir/value.h"
#include "shader_recompiler/ir_opt/passes.h"

namespace Shader::Optimization {
namespace {
std::pair<IR::U32, IR::U32> Unpack(IR::IREmitter& ir, const IR::Value& packed) {
    if (packed.IsImmediate()) {
        const u64 value{packed.U64()};
        return {
            ir.Imm32(static_cast<u32>(value)),
            ir.Imm32(static_cast<u32>(value >> 32)),
        };
    } else {
        return std::pair<IR::U32, IR::U32>{
            ir.CompositeExtract(packed, 0u),
            ir.CompositeExtract(packed, 1u),
        };
    }
}

void IAdd64To32(IR::Block& block, IR::Inst& inst) {
    if (inst.HasAssociatedPseudoOperation()) {
        throw NotImplementedException("IAdd64 emulation with pseudo instructions");
    }
    IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
    const auto [a_lo, a_hi]{Unpack(ir, inst.Arg(0))};
    const auto [b_lo, b_hi]{Unpack(ir, inst.Arg(1))};

    const IR::U32 ret_lo{ir.IAdd(a_lo, b_lo)};
    const IR::U32 carry{ir.Select(ir.GetCarryFromOp(ret_lo), ir.Imm32(1u), ir.Imm32(0u))};

    const IR::U32 ret_hi{ir.IAdd(ir.IAdd(a_hi, b_hi), carry)};
    inst.ReplaceUsesWith(ir.CompositeConstruct(ret_lo, ret_hi));
}

void ISub64To32(IR::Block& block, IR::Inst& inst) {
    if (inst.HasAssociatedPseudoOperation()) {
        throw NotImplementedException("ISub64 emulation with pseudo instructions");
    }
    IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
    const auto [a_lo, a_hi]{Unpack(ir, inst.Arg(0))};
    const auto [b_lo, b_hi]{Unpack(ir, inst.Arg(1))};

    const IR::U32 ret_lo{ir.ISub(a_lo, b_lo)};
    const IR::U1 underflow{ir.IGreaterThan(ret_lo, a_lo, false)};
    const IR::U32 underflow_bit{ir.Select(underflow, ir.Imm32(1u), ir.Imm32(0u))};

    const IR::U32 ret_hi{ir.ISub(ir.ISub(a_hi, b_hi), underflow_bit)};
    inst.ReplaceUsesWith(ir.CompositeConstruct(ret_lo, ret_hi));
}

void INeg64To32(IR::Block& block, IR::Inst& inst) {
    if (inst.HasAssociatedPseudoOperation()) {
        throw NotImplementedException("INeg64 emulation with pseudo instructions");
    }
    IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
    auto [lo, hi]{Unpack(ir, inst.Arg(0))};
    lo = ir.BitwiseNot(lo);
    hi = ir.BitwiseNot(hi);

    lo = ir.IAdd(lo, ir.Imm32(1));

    const IR::U32 carry{ir.Select(ir.GetCarryFromOp(lo), ir.Imm32(1u), ir.Imm32(0u))};
    hi = ir.IAdd(hi, carry);

    inst.ReplaceUsesWith(ir.CompositeConstruct(lo, hi));
}

void ShiftLeftLogical64To32(IR::Block& block, IR::Inst& inst) {
    if (inst.HasAssociatedPseudoOperation()) {
        throw NotImplementedException("ShiftLeftLogical64 emulation with pseudo instructions");
    }
    IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
    const auto [lo, hi]{Unpack(ir, inst.Arg(0))};
    const IR::U32 shift{inst.Arg(1)};

    const IR::U32 shifted_lo{ir.ShiftLeftLogical(lo, shift)};
    const IR::U32 shifted_hi{ir.ShiftLeftLogical(hi, shift)};

    const IR::U32 inv_shift{ir.ISub(shift, ir.Imm32(32))};
    const IR::U1 is_long{ir.IGreaterThanEqual(inv_shift, ir.Imm32(0), true)};
    const IR::U1 is_zero{ir.IEqual(shift, ir.Imm32(0))};

    const IR::U32 long_ret_lo{ir.Imm32(0)};
    const IR::U32 long_ret_hi{ir.ShiftLeftLogical(lo, inv_shift)};

    const IR::U32 shift_complement{ir.ISub(ir.Imm32(32), shift)};
    const IR::U32 lo_extract{ir.BitFieldExtract(lo, shift_complement, shift, false)};
    const IR::U32 short_ret_lo{shifted_lo};
    const IR::U32 short_ret_hi{ir.BitwiseOr(shifted_hi, lo_extract)};

    const IR::U32 zero_ret_lo{lo};
    const IR::U32 zero_ret_hi{hi};

    const IR::U32 non_zero_lo{ir.Select(is_long, long_ret_lo, short_ret_lo)};
    const IR::U32 non_zero_hi{ir.Select(is_long, long_ret_hi, short_ret_hi)};

    const IR::U32 ret_lo{ir.Select(is_zero, zero_ret_lo, non_zero_lo)};
    const IR::U32 ret_hi{ir.Select(is_zero, zero_ret_hi, non_zero_hi)};
    inst.ReplaceUsesWith(ir.CompositeConstruct(ret_lo, ret_hi));
}

void ShiftRightLogical64To32(IR::Block& block, IR::Inst& inst) {
    if (inst.HasAssociatedPseudoOperation()) {
        throw NotImplementedException("ShiftRightLogical64 emulation with pseudo instructions");
    }
    IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
    const auto [lo, hi]{Unpack(ir, inst.Arg(0))};
    const IR::U32 shift{inst.Arg(1)};

    const IR::U32 shifted_lo{ir.ShiftRightLogical(lo, shift)};
    const IR::U32 shifted_hi{ir.ShiftRightLogical(hi, shift)};

    const IR::U32 inv_shift{ir.ISub(shift, ir.Imm32(32))};
    const IR::U1 is_long{ir.IGreaterThanEqual(inv_shift, ir.Imm32(0), true)};
    const IR::U1 is_zero{ir.IEqual(shift, ir.Imm32(0))};

    const IR::U32 long_ret_hi{ir.Imm32(0)};
    const IR::U32 long_ret_lo{ir.ShiftRightLogical(hi, inv_shift)};

    const IR::U32 shift_complement{ir.ISub(ir.Imm32(32), shift)};
    const IR::U32 short_hi_extract{ir.BitFieldExtract(hi, ir.Imm32(0), shift)};
    const IR::U32 short_ret_hi{shifted_hi};
    const IR::U32 short_ret_lo{
        ir.BitFieldInsert(shifted_lo, short_hi_extract, shift_complement, shift)};

    const IR::U32 zero_ret_lo{lo};
    const IR::U32 zero_ret_hi{hi};

    const IR::U32 non_zero_lo{ir.Select(is_long, long_ret_lo, short_ret_lo)};
    const IR::U32 non_zero_hi{ir.Select(is_long, long_ret_hi, short_ret_hi)};

    const IR::U32 ret_lo{ir.Select(is_zero, zero_ret_lo, non_zero_lo)};
    const IR::U32 ret_hi{ir.Select(is_zero, zero_ret_hi, non_zero_hi)};
    inst.ReplaceUsesWith(ir.CompositeConstruct(ret_lo, ret_hi));
}

void ShiftRightArithmetic64To32(IR::Block& block, IR::Inst& inst) {
    if (inst.HasAssociatedPseudoOperation()) {
        throw NotImplementedException("ShiftRightArithmetic64 emulation with pseudo instructions");
    }
    IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
    const auto [lo, hi]{Unpack(ir, inst.Arg(0))};
    const IR::U32 shift{inst.Arg(1)};

    const IR::U32 shifted_lo{ir.ShiftRightLogical(lo, shift)};
    const IR::U32 shifted_hi{ir.ShiftRightArithmetic(hi, shift)};

    const IR::U32 sign_extension{ir.ShiftRightArithmetic(hi, ir.Imm32(31))};

    const IR::U32 inv_shift{ir.ISub(shift, ir.Imm32(32))};
    const IR::U1 is_long{ir.IGreaterThanEqual(inv_shift, ir.Imm32(0), true)};
    const IR::U1 is_zero{ir.IEqual(shift, ir.Imm32(0))};

    const IR::U32 long_ret_hi{sign_extension};
    const IR::U32 long_ret_lo{ir.ShiftRightArithmetic(hi, inv_shift)};

    const IR::U32 shift_complement{ir.ISub(ir.Imm32(32), shift)};
    const IR::U32 short_hi_extract(ir.BitFieldExtract(hi, ir.Imm32(0), shift));
    const IR::U32 short_ret_hi{shifted_hi};
    const IR::U32 short_ret_lo{
        ir.BitFieldInsert(shifted_lo, short_hi_extract, shift_complement, shift)};

    const IR::U32 zero_ret_lo{lo};
    const IR::U32 zero_ret_hi{hi};

    const IR::U32 non_zero_lo{ir.Select(is_long, long_ret_lo, short_ret_lo)};
    const IR::U32 non_zero_hi{ir.Select(is_long, long_ret_hi, short_ret_hi)};

    const IR::U32 ret_lo{ir.Select(is_zero, zero_ret_lo, non_zero_lo)};
    const IR::U32 ret_hi{ir.Select(is_zero, zero_ret_hi, non_zero_hi)};
    inst.ReplaceUsesWith(ir.CompositeConstruct(ret_lo, ret_hi));
}

void Lower(IR::Block& block, IR::Inst& inst) {
    switch (inst.GetOpcode()) {
    case IR::Opcode::PackUint2x32:
    case IR::Opcode::UnpackUint2x32:
        return inst.ReplaceOpcode(IR::Opcode::Identity);
    case IR::Opcode::IAdd64:
        return IAdd64To32(block, inst);
    case IR::Opcode::ISub64:
        return ISub64To32(block, inst);
    case IR::Opcode::INeg64:
        return INeg64To32(block, inst);
    case IR::Opcode::ShiftLeftLogical64:
        return ShiftLeftLogical64To32(block, inst);
    case IR::Opcode::ShiftRightLogical64:
        return ShiftRightLogical64To32(block, inst);
    case IR::Opcode::ShiftRightArithmetic64:
        return ShiftRightArithmetic64To32(block, inst);
    case IR::Opcode::SharedAtomicExchange64:
        return inst.ReplaceOpcode(IR::Opcode::SharedAtomicExchange32x2);
    case IR::Opcode::GlobalAtomicIAdd64:
        return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicIAdd32x2);
    case IR::Opcode::GlobalAtomicSMin64:
        return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicSMin32x2);
    case IR::Opcode::GlobalAtomicUMin64:
        return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicUMin32x2);
    case IR::Opcode::GlobalAtomicSMax64:
        return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicSMax32x2);
    case IR::Opcode::GlobalAtomicUMax64:
        return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicUMax32x2);
    case IR::Opcode::GlobalAtomicAnd64:
        return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicAnd32x2);
    case IR::Opcode::GlobalAtomicOr64:
        return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicOr32x2);
    case IR::Opcode::GlobalAtomicXor64:
        return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicXor32x2);
    case IR::Opcode::GlobalAtomicExchange64:
        return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicExchange32x2);
    default:
        break;
    }
}
} // Anonymous namespace

void LowerInt64ToInt32(IR::Program& program) {
    const auto end{program.post_order_blocks.rend()};
    for (auto it = program.post_order_blocks.rbegin(); it != end; ++it) {
        IR::Block* const block{*it};
        for (IR::Inst& inst : block->Instructions()) {
            Lower(*block, inst);
        }
    }
}

} // namespace Shader::Optimization


code:
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later

#pragma once

#include "shader_recompiler/environment.h"
#include "shader_recompiler/frontend/ir/program.h"

namespace Shader {
struct HostTranslateInfo;
}

namespace Shader::Optimization {

void CollectShaderInfoPass(Environment& env, IR::Program& program);
void ConditionalBarrierPass(IR::Program& program);
void ConstantPropagationPass(Environment& env, IR::Program& program);
void DeadCodeEliminationPass(IR::Program& program);
void GlobalMemoryToStorageBufferPass(IR::Program& program, const HostTranslateInfo& host_info);
void IdentityRemovalPass(IR::Program& program);
void LowerFp64ToFp32(IR::Program& program);
void LowerFp16ToFp32(IR::Program& program);
void LowerInt64ToInt32(IR::Program& program);
void RescalingPass(IR::Program& program);
void SsaRewritePass(IR::Program& program);
void PositionPass(Environment& env, IR::Program& program);
void TexturePass(Environment& env, IR::Program& program, const HostTranslateInfo& host_info);
void LayerPass(IR::Program& program, const HostTranslateInfo& host_info);
void VendorWorkaroundPass(IR::Program& program);
void VerificationPass(const IR::Program& program);

// Dual Vertex
void VertexATransformPass(IR::Program& program);
void VertexBTransformPass(IR::Program& program);
void JoinTextureInfo(Info& base, Info& source);
void JoinStorageInfo(Info& base, Info& source);

} // namespace Shader::Optimization


code:
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later

#include <boost/container/small_vector.hpp>

#include "shader_recompiler/frontend/ir/basic_block.h"
#include "shader_recompiler/frontend/ir/ir_emitter.h"
#include "shader_recompiler/frontend/ir/value.h"
#include "shader_recompiler/ir_opt/passes.h"

namespace Shader::Optimization {

namespace {
struct PositionInst {
    IR::Inst* inst;
    IR::Block* block;
    IR::Attribute attr;
};
using PositionInstVector = boost::container::small_vector<PositionInst, 24>;
} // Anonymous namespace

void PositionPass(Environment& env, IR::Program& program) {
    if (env.ShaderStage() != Stage::VertexB || env.ReadViewportTransformState()) {
        return;
    }

    Info& info{program.info};
    info.uses_render_area = true;

    PositionInstVector to_replace;
    for (IR::Block* const block : program.post_order_blocks) {
        for (IR::Inst& inst : block->Instructions()) {
            switch (inst.GetOpcode()) {
            case IR::Opcode::SetAttribute: {
                const IR::Attribute attr{inst.Arg(0).Attribute()};
                switch (attr) {
                case IR::Attribute::PositionX:
                case IR::Attribute::PositionY: {
                    to_replace.push_back(PositionInst{.inst = &inst, .block = block, .attr = attr});
                    break;
                }
                default:
                    break;
                }
                break;
            }
            default:
                break;
            }
        }
    }

    for (PositionInst& position_inst : to_replace) {
        IR::IREmitter ir{*position_inst.block,
                         IR::Block::InstructionList::s_iterator_to(*position_inst.inst)};
        const IR::F32 value(position_inst.inst->Arg(1));
        const IR::F32F64 scale(ir.Imm32(2.f));
        const IR::F32 negative_one{ir.Imm32(-1.f)};
        switch (position_inst.attr) {
        case IR::Attribute::PositionX: {
            position_inst.inst->SetArg(
                1,
                ir.FPFma(value, ir.FPMul(ir.FPRecip(ir.RenderAreaWidth()), scale), negative_one));
            break;
        }
        case IR::Attribute::PositionY: {
            position_inst.inst->SetArg(
                1,
                ir.FPFma(value, ir.FPMul(ir.FPRecip(ir.RenderAreaHeight()), scale), negative_one));
            break;
        }
        default:
            break;
        }
    }
}
} // namespace Shader::Optimization