source
stringclasses 1
value | dataset
stringclasses 2
values | id
stringlengths 7
9
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stringlengths 12
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| task_type
stringclasses 2
values | content
stringlengths 36
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| metadata
dict |
|---|---|---|---|---|---|---|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_400
|
Prob116_m2014_q3_ifc.txt
|
code_completion
|
module TopModule (
input [4:1] x,
output logic f
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob116_m2014_q3_ifc.txt",
"file_size": 57
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_401
|
Prob120_fsm3s_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input in,
input reset,
output out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob120_fsm3s_ifc.txt",
"file_size": 76
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_402
|
Prob063_review2015_shiftcount_prompt.txt
|
code_completion
|
Build a four-bit shift register that also acts as a down counter. Data is
shifted in most-significant-bit first when shift_ena is 1. The number
currently in the shift register is decremented when count_ena is 1. Since
the full system doesn't ever use shift_ena and count_ena together, it
does not matter what your circuit does if both control inputs are 1 (This
mainly means that it doesn't matter which case gets higher priority).
module TopModule (
input clk,
input shift_ena,
input count_ena,
input data,
output reg [3:0] q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob063_review2015_shiftcount_prompt.txt",
"file_size": 543
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_403
|
Prob142_lemmings2_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob142_lemmings2_ifc.txt",
"file_size": 162
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_404
|
Prob108_rule90_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input load,
input [511:0] data,
output reg [511:0] q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob108_rule90_ifc.txt",
"file_size": 95
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_405
|
Prob028_m2014_q4a_ifc.txt
|
code_completion
|
module TopModule (
input d,
input ena,
output logic q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob028_m2014_q4a_ifc.txt",
"file_size": 64
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_406
|
Prob036_ringer_prompt.txt
|
code_completion
|
Suppose you are designing a circuit to control a cellphone's ringer and
vibration motor. Whenever the phone needs to ring from an incoming call
(input ring), your circuit must either turn on the ringer (output ringer
= 1) or the motor (output motor = 1), but not both. If the phone is in
vibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn
on the ringer.
module TopModule (
input ring,
input vibrate_mode,
output ringer,
output motor
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob036_ringer_prompt.txt",
"file_size": 470
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_407
|
Prob034_dff8_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input [7:0] d,
output reg [7:0] q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob034_dff8_ifc.txt",
"file_size": 74
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_408
|
Prob093_ece241_2014_q3_prompt.txt
|
code_completion
|
For the following Karnaugh map, give the circuit implementation using one
4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using
as few as possible. You are not allowed to use any other logic gate and
you must use _a_ and _b_ as the multiplexer selector inputs, as shown on
the 4-to-1 multiplexer below.
ab
cd 00 01 11 10
00 | 0 | 0 | 0 | 1 |
01 | 1 | 0 | 0 | 0 |
11 | 1 | 0 | 1 | 1 |
10 | 1 | 0 | 0 | 1 |
Consider a block diagram with inputs 'c' and 'd' going into a module
called "top_module". This "top_module" has four outputs, mux_in[3:0],
that connect to a four input mux. The mux takes as input {a,b} and ab =
00 is connected to mux_in[0], ab=01 is connected to mux_in[1], and so in.
You are implementing in Verilog just the portion labelled "top_module",
such that the entire circuit (including the 4-to-1 mux) implements the
K-map.
module TopModule (
input c,
input d,
output [3:0] mux_in
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob093_ece241_2014_q3_prompt.txt",
"file_size": 951
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_409
|
Prob146_fsm_serialdata_prompt.txt
|
code_completion
|
In many (older) serial communications protocols, each data byte is sent
along with a start bit and a stop bit, to help the receiver delimit bytes
from the stream of bits. One common scheme is to use one start bit (0), 8
data bits, and 1 stop bit (1). The line is also at logic 1 when nothing
is being transmitted (idle). Design a finite state machine that will
identify when bytes have been correctly received when given a stream of
bits. It needs to identify the start bit, wait for all 8 data bits, then
verify that the stop bit was correct. The module will also output the
correctly- received data byte. out_byte needs to be valid when done is 1,
and is don't-care otherwise.If the stop bit does not appear when
expected, the FSM must wait until it finds a stop bit before attempting
to receive the next byte. Include a active-high synchronous reset. Note
that the serial protocol sends the least significant bit first. It should
assert done each time it finds a stop bit.
module TopModule (
input clk,
input in,
input reset,
output [7:0] out_byte,
output done
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob146_fsm_serialdata_prompt.txt",
"file_size": 1080
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_410
|
Prob049_m2014_q4b_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input d,
input ar,
output logic q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob049_m2014_q4b_ifc.txt",
"file_size": 76
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_411
|
Prob054_edgedetect_prompt.txt
|
code_completion
|
For each bit in an 8-bit vector, detect when the input signal changes
from 0 in one clock cycle to 1 the next (similar to positive edge
detection). The output bit should be set the cycle after a 0 to 1
transition occurs.
module TopModule (
input clk,
input [7:0] in,
output reg [7:0] pedge
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob054_edgedetect_prompt.txt",
"file_size": 302
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_412
|
Prob019_m2014_q4f_prompt.txt
|
code_completion
|
Implement the following circuit in Verilog. Two inputs (in1 and in2) go
to an AND gate, but the in2 input to the AND gate has a bubble. The
output of the AND gate is connected to 'out'.
module TopModule (
input in1,
input in2,
output logic out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob019_m2014_q4f_prompt.txt",
"file_size": 256
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_413
|
Prob101_circuit4_prompt.txt
|
code_completion
|
This is a combinational circuit. Read the simulation waveforms to
determine what the circuit does, then implement it.
time a b c d q
0ns 0 0 0 0 0
5ns 0 0 0 0 0
10ns 0 0 0 0 0
15ns 0 0 0 0 0
20ns 0 0 0 1 0
25ns 0 0 1 0 1
30ns 0 0 1 1 1
35ns 0 1 0 0 1
40ns 0 1 0 1 1
45ns 0 1 1 0 1
50ns 0 1 1 1 1
55ns 1 0 0 0 0
60ns 1 0 0 1 0
65ns 1 0 1 0 1
70ns 1 0 1 1 1
75ns 1 1 0 0 1
80ns 1 1 0 1 1
85ns 1 1 1 0 1
90ns 1 1 1 1 1
module TopModule (
input a,
input b,
input c,
input d,
output q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob101_circuit4_prompt.txt",
"file_size": 639
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_414
|
Prob056_ece241_2013_q7_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input j,
input k,
output reg Q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob056_ece241_2013_q7_ifc.txt",
"file_size": 73
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_415
|
Prob109_fsm1_prompt.txt
|
code_completion
|
Consider the follow Moore machine with the diagram described below:
B (1) --0--> A
B (1) --1--> B
A (0) --0--> B
A (0) --1--> A
Write Verilog implementing this state machine. It should asynchronously
reset into state B if reset if high.
module TopModule (
input clk,
input in,
input areset,
output out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob109_fsm1_prompt.txt",
"file_size": 326
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_416
|
Prob111_fsm2s_prompt.txt
|
code_completion
|
This is a Moore state machine with two states, two inputs, and one
output. Implement this state machine in Verilog. Reset is an active-high
synchronous reset to state OFF.
OFF (out=0) --j=0--> OFF
OFF (out=0) --j=1--> ON
ON (out=1) --k=0--> ON
ON (out=1) --k=1--> OFF
module TopModule (
input clk,
input j,
input k,
input reset,
output out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob111_fsm2s_prompt.txt",
"file_size": 367
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_417
|
Prob117_circuit9_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input a,
output reg [2:0] q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob117_circuit9_ifc.txt",
"file_size": 68
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_418
|
Prob119_fsm3_prompt.txt
|
code_completion
|
The following is the state transition table for a Moore state machine
with one input, one output, and four states. Implement this state
machine. Include a positive edge triggered asynchronous reset that resets
the FSM to state A.
state | next state in=0, next state in=1 | output
A | A, B | 0
B | C, B | 0
C | A, D | 0
D | C, B | 1
module TopModule (
input clk,
input in,
input areset,
output out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob119_fsm3_prompt.txt",
"file_size": 550
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_419
|
Prob073_dff16e_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output reg [15:0] q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob073_dff16e_ifc.txt",
"file_size": 115
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_420
|
Prob029_m2014_q4g_prompt.txt
|
code_completion
|
Implement in Verilog the following circuit: A two-input XNOR (connected
to 'in1' and 'in2) has an output connected to the input of a two-input
XOR. The second input of the XOR is 'in3.' The output of the XOR is
'out'.
module TopModule (
input in1,
input in2,
input in3,
output logic out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob029_m2014_q4g_prompt.txt",
"file_size": 301
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_421
|
Prob154_fsm_ps2data_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob154_fsm_ps2data_ifc.txt",
"file_size": 110
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_422
|
Prob137_fsm_serial_prompt.txt
|
code_completion
|
In many (older) serial communications protocols, each data byte is sent
along with a start bit and a stop bit, to help the receiver delimit bytes
from the stream of bits. One common scheme is to use one start bit (0), 8
data bits, and 1 stop bit (1). The line is also at logic 1 when nothing
is being transmitted (idle). Design a finite state machine that will
identify when bytes have been correctly received when given a stream of
bits. It needs to identify the start bit, wait for all 8 data bits, then
verify that the stop bit was correct. If the stop bit does not appear
when expected, the FSM must wait until it finds a stop bit before
attempting to receive the next byte. Include a active-high synchronous
reset. Note that the serial protocol sends the least significant bit
first.
module TopModule (
input clk,
input in,
input reset,
output done
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob137_fsm_serial_prompt.txt",
"file_size": 868
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_423
|
Prob005_notgate_ifc.txt
|
code_completion
|
module TopModule (
input in,
output out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob005_notgate_ifc.txt",
"file_size": 48
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_424
|
Prob060_m2014_q4k_prompt.txt
|
code_completion
|
Implement a shift register with four D flops. Reset is active-low
synchronous resettable.
module TopModule (
input clk,
input resetn,
input in,
output out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob060_m2014_q4k_prompt.txt",
"file_size": 169
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_425
|
Prob039_always_if_prompt.txt
|
code_completion
|
Build a 2-to-1 mux that chooses between a and b. Choose b if both sel_b1
and sel_b2 are true. Otherwise, choose a. Do the same twice, once using
assign statements and once using a procedural if statement.
module TopModule (
input a,
input b,
input sel_b1,
input sel_b2,
output out_assign,
output reg out_always
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob039_always_if_prompt.txt",
"file_size": 329
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_426
|
Prob068_countbcd_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input reset,
output [3:1] ena,
output reg [15:0] q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob068_countbcd_ifc.txt",
"file_size": 93
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_427
|
Prob142_lemmings2_prompt.txt
|
code_completion
|
The game Lemmings involves critters with fairly simple brains. So simple
that we are going to model it using a finite state machine. In the
Lemmings' 2D world, Lemmings can be in one of two states: walking left
(walk_left is 1) or walking right (walk_right is 1). It will switch
directions if it hits an obstacle. In particular, if a Lemming is bumped
on the left (by receiving a 1 on bump_left), it will walk right. If it's
bumped on the right (by receiving a 1 on bump_right), it will walk left.
If it's bumped on both sides at the same time, it will still switch
directions.
In addition to walking left and right and changing direction when bumped,
when ground=0, the Lemming will fall and say "aaah!". When the ground
reappears (ground=1), the Lemming will resume walking in the same
direction as before the fall. Being bumped while falling does not affect
the walking direction, and being bumped in the same cycle as ground
disappears (but not yet falling), or when the ground reappears while
still falling, also does not affect the walking direction.
Implement a Moore state machine that models this behaviour. areset is
positive edge triggered asynchronous reseting the Lemming machine to walk
left.
module TopModule (
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob142_lemmings2_prompt.txt",
"file_size": 1373
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_428
|
Prob051_gates4_ifc.txt
|
code_completion
|
module TopModule (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob051_gates4_ifc.txt",
"file_size": 93
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_429
|
Prob151_review2015_fsm_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input reset,
input data,
output reg shift_ena,
output reg counting,
input done_counting,
output reg done,
input ack
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob151_review2015_fsm_ifc.txt",
"file_size": 166
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_430
|
Prob041_dff8r_prompt.txt
|
code_completion
|
Create 8 D flip-flops with active high synchronous reset setting the
output to zero. All DFFs should be triggered by the positive edge of clk.
module TopModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob041_dff8r_prompt.txt",
"file_size": 234
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_431
|
Prob155_lemmings4_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob155_lemmings4_ifc.txt",
"file_size": 193
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_432
|
Prob048_m2014_q4c_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input d,
input r,
output logic q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob048_m2014_q4c_ifc.txt",
"file_size": 75
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_433
|
Prob105_rotate100_prompt.txt
|
code_completion
|
Build a 100-bit left/right rotator, with synchronous load and left/right
enable. A rotator shifts-in the shifted-out bit from the other end of the
register, unlike a shifter that discards the shifted-out bit and shifts
in a zero. If enabled, a rotator rotates the bits around and does not
modify/discard them.
(1) load: Loads shift register with data[99:0] instead of rotating.
Synchronous active high.
(2) ena[1:0]: Synchronous. Chooses whether and which direction to
rotate:
(a) 2'b01 rotates right by one bit,
(b) 2'b10 rotates left by one bit,
(c) 2'b00 and 2'b11 do not rotate.
(3) q: The contents of the rotator.
module TopModule (
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob105_rotate100_prompt.txt",
"file_size": 772
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_434
|
Prob150_review2015_fsmonehot_prompt.txt
|
code_completion
|
Given the following Moore state machine with 3 input (d, done_counting,
ack) and 3 outputs (shift_ena, counting, done). Unless otherwise stated in
the diagram below, assume outputs are 0 and inputs are don't cares.
state (output) --input--> next state
-------------------------------------------
S () --d=0--> S
S () --d=1--> S1
S1 () --d=0--> S
S1 () --d=1--> S11
S11 () --d=0--> S110
S11 () --d=1--> S11
S110 () --d=0--> S
S110 () --d=1--> B0
B0 (shift_ena=1) --(always go to next cycle)--> B1
B1 (shift_ena=1) --(always go to next cycle)--> B2
B2 (shift_ena=1) --(always go to next cycle)--> B3
B3 (shift_ena=1) --(always go to next cycle)--> Count
Count (counting=1) --done_counting=0--> Count
Count (counting=1) --done_counting=1--> Wait
Wait (done=1) --ack=0--> Wait
Wait (done=1) --ack=1--> S
At reset, the state machine starts in state "S". Derive next-state logic
equations and output logic equations by inspection assuming the following
one-hot encoding is used: (S, S1, S11, S110, B0, B1, B2, B3, Count, Wait)
= (10'b0000000001, 10'b0000000010, 10'b0000000100, ... , 10'b1000000000)
Derive state transition and output logic equations by inspection assuming
a one-hot encoding. Implement only the state transition logic and output
logic (the combinational logic portion) for this state machine.
Write code that generates the following signals:
- B3_next -- Assert when next-state is B3 state
- S_next -- Assert when next-state is S state
- S1_next -- Assert when next-state is S1 state
- Count_next -- Assert when next-state is Count state
- Wait_next -- Assert when next-state is Wait state
- done -- output logic
- counting -- output logic
- shift_ena -- output logic
module TopModule (
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob150_review2015_fsmonehot_prompt.txt",
"file_size": 2138
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_435
|
Prob154_fsm_ps2data_prompt.txt
|
code_completion
|
We want a finite state machine that will search for message boundaries
when given an input byte stream. The algorithm we'll use is to discard
bytes until we see one with in[3]=1. We then assume that this is byte 1
of a message, and signal the receipt of a message once all 3 bytes have
been received (done). The FSM should signal done in the cycle immediately
after the third byte of each message was successfully received.
Implement the datapath module that will output the 24-bit (3 byte)
message whenever a packet is received (out_bytes[23:16] is the first
byte, out_bytes[15:8] is the second byte, etc.). The reset signal is
active high synchronous. out_bytes needs to be valid whenever the done
signal is asserted. You may output anything at other times (i.e.,
don't-care).
Waveform example:
time clk rst in done out_bytes
0ns 0 1 0 x x
5ns 1 1 0 0 x
10ns 0 1 0 0 x
15ns 1 0 2c 0 x
20ns 0 0 2c 0 x
25ns 1 0 81 0 x
30ns 0 0 81 0 x
35ns 1 0 9 0 x
40ns 0 0 9 0 x
45ns 1 0 6b 1 2c8109
50ns 0 0 6b 1 2c8109
55ns 1 0 d 0 x
60ns 0 0 d 0 x
65ns 1 0 8d 0 x
70ns 0 0 8d 0 x
75ns 1 0 6d 1 6b0d8d
80ns 0 0 6d 1 6b0d8d
85ns 1 0 12 0 x
90ns 0 0 12 0 x
95ns 1 0 1 0 x
100ns 0 0 1 0 x
105ns 1 0 d 1 6d1201
110ns 0 0 d 1 6d1201
115ns 1 0 76 0 x
120ns 0 0 76 0 x
125ns 1 0 3d 0 x
130ns 0 0 3d 0 x
135ns 1 0 ed 1 d763d
140ns 0 0 ed 1 d763d
145ns 1 0 8c 0 x
150ns 0 0 8c 0 x
155ns 1 0 f9 0 x
160ns 0 0 f9 0 x
165ns 1 0 ce 1 ed8cf9
170ns 0 0 ce 1 ed8cf9
175ns 1 0 c5 0 x
180ns 0 0 c5 0 x
185ns 1 0 aa 0 x
190ns 0 0 aa 0 x
module TopModule (
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob154_fsm_ps2data_prompt.txt",
"file_size": 2236
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_436
|
Prob055_conditional_ifc.txt
|
code_completion
|
module TopModule (
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output reg [7:0] min
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob055_conditional_ifc.txt",
"file_size": 114
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_437
|
Prob096_review2015_fsmseq_prompt.txt
|
code_completion
|
Build a finite-state machine that searches for the sequence 1101 in an
input bit stream. When the sequence is found, it should set
start_shifting to 1, forever, until reset. Reset is active high
synchronous.
module TopModule (
input clk,
input reset,
input data,
output start_shifting
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob096_review2015_fsmseq_prompt.txt",
"file_size": 299
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_438
|
Prob132_always_if2_prompt.txt
|
code_completion
|
Fix any and all bugs in this code:
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving );
always @(*) begin
if (cpu_overheated)
shut_off_computer = 1;
end
always @(*) begin
if (~arrived)
keep_driving = ~gas_tank_empty;
end
endmodule
module TopModule (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob132_always_if2_prompt.txt",
"file_size": 586
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_439
|
Prob038_count15_prompt.txt
|
code_completion
|
Build a 4-bit binary counter that counts from 0 through 15, inclusive,
with a period of 16. The reset input is active high synchronous, and
should reset the counter to 0.
module TopModule (
input clk,
input reset,
output reg [3:0] q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob038_count15_prompt.txt",
"file_size": 245
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_440
|
Prob032_vector0_ifc.txt
|
code_completion
|
module TopModule (
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob032_vector0_ifc.txt",
"file_size": 101
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_441
|
Prob011_norgate_prompt.txt
|
code_completion
|
Create a module that implements a NOR gate.
module TopModule (
input a,
input b,
output out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob011_norgate_prompt.txt",
"file_size": 104
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_442
|
Prob020_mt2015_eq2_prompt.txt
|
code_completion
|
Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and
produces an output z. The value of z should be 1 if A = B, otherwise z
should be 0.
module TopModule (
input [1:0] A,
input [1:0] B,
output z
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob020_mt2015_eq2_prompt.txt",
"file_size": 220
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_443
|
Prob059_wire4_prompt.txt
|
code_completion
|
Create a module with 3 inputs and 4 outputs that behaves like wires that
makes these connections:
a -> w
b -> x
b -> y
c -> z
module TopModule (
input a,
input b,
input c,
output w,
output x,
output y,
output z
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob059_wire4_prompt.txt",
"file_size": 240
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_444
|
Prob140_fsm_hdlc_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input reset,
input in,
output disc,
output flag,
output err
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob140_fsm_hdlc_ifc.txt",
"file_size": 106
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_445
|
Prob134_2014_q3c_prompt.txt
|
code_completion
|
Given the state-assigned table shown below, implement the logic functions
Y[0] and z.
Present state input y[2:0] | Next state Y[2:0] when x=0, Next state Y[2:0] when x=1 | Output z
000 | 000, 001 | 0
001 | 001, 100 | 0
010 | 010, 001 | 0
011 | 001, 010 | 1
100 | 011, 100 | 1
module TopModule (
input clk,
input x,
input [2:0] y,
output reg Y0,
output reg z
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob134_2014_q3c_prompt.txt",
"file_size": 393
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_446
|
Prob061_2014_q4a_prompt.txt
|
code_completion
|
Consider an n-bit shift register circuit. Inputs E are for enabling
shift, R for value to load, L is asserted when it should load, and w is
the input to the first stage of the shift register. Write a Verilog
module named top_module for one stage of this circuit, including both the
flip-flop and multiplexers.
module TopModule (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob061_2014_q4a_prompt.txt",
"file_size": 407
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_447
|
Prob152_lemmings3_prompt.txt
|
code_completion
|
The game Lemmings involves critters with fairly simple brains. So simple
that we are going to model it using a finite state machine. In the
Lemmings' 2D world, Lemmings can be in one of two states: walking left
(walk_left is 1) or walking right (walk_right is 1). It will switch
directions if it hits an obstacle. In particular, if a Lemming is bumped
on the left (by receiving a 1 on bump_left), it will walk right. If it's
bumped on the right (by receiving a 1 on bump_right), it will walk left.
If it's bumped on both sides at the same time, it will still switch
directions.
In addition to walking left and right and changing direction when bumped,
when ground=0, the Lemming will fall and say "aaah!". When the ground
reappears (ground=1), the Lemming will resume walking in the same
direction as before the fall. Being bumped while falling does not affect
the walking direction, and being bumped in the same cycle as ground
disappears (but not yet falling), or when the ground reappears while
still falling, also does not affect the walking direction.
In addition to walking and falling, Lemmings can sometimes be told to do
useful things, like dig (it starts digging when dig=1). A Lemming can dig
if it is currently walking on ground (ground=1 and not falling), and will
continue digging until it reaches the other side (ground=0). At that
point, since there is no ground, it will fall (aaah!), then continue
walking in its original direction once it hits ground again. As with
falling, being bumped while digging has no effect, and being told to dig
when falling or when there is no ground is ignored. (In other words, a
walking Lemming can fall, dig, or switch directions. If more than one of
these conditions are satisfied, fall has higher precedence than dig,
which has higher precedence than switching directions.)
Implement a Moore state machine that models this behaviour. areset is
positive edge triggered asynchronous reseting the Lemming machine to walk
left.
module TopModule (
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob152_lemmings3_prompt.txt",
"file_size": 2175
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_448
|
Prob086_lfsr5_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input reset,
output reg [4:0] q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob086_lfsr5_ifc.txt",
"file_size": 72
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_449
|
Prob115_shift18_prompt.txt
|
code_completion
|
Build a 64-bit arithmetic shift register, with synchronous load. The
shifter can shift both left and right, and by 1 or 8 bit positions,
selected by "amount." Assume the right shit is an arithmetic right shift.
Signals are defined as below:
(1) load: Loads shift register with data[63:0] instead of shifting.
Active high.
(2) ena: Chooses whether to shift. Active high.
(3) amount: Chooses which direction and how much to shift.
(a) 2'b00: shift left by 1 bit.
(b) 2'b01: shift left by 8 bits.
(c) 2'b10: shift right by 1 bit.
(d) 2'b11: shift right by 8 bits.
(4) q: The contents of the shifter.
module TopModule (
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob115_shift18_prompt.txt",
"file_size": 768
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_450
|
Prob072_thermostat_prompt.txt
|
code_completion
|
A heating/cooling thermostat controls both a heater (during winter) and
an air conditioner (during summer). Implement a circuit that will turn on
and off the heater, air conditioning, and blower fan as appropriate. The
thermostat can be in one of two modes: heating (mode = 1) and cooling
(mode = 0). In heating mode, turn the heater on when it is too cold
(too_cold = 1) but do not use the air conditioner. In cooling mode, turn
the air conditioner on when it is too hot (too_hot = 1), but do not turn
on the heater. When the heater or air conditioner are on, also turn on
the fan to circulate the air. In addition, the user can also request the
fan to turn on (fan_on = 1), even if the heater and air conditioner are
off.
module TopModule (
input mode,
input too_cold,
input too_hot,
input fan_on,
output heater,
output aircon,
output fan
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob072_thermostat_prompt.txt",
"file_size": 861
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_451
|
Prob065_7420_ifc.txt
|
code_completion
|
module TopModule (
input p1a,
input p1b,
input p1c,
input p1d,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob065_7420_ifc.txt",
"file_size": 154
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_452
|
Prob061_2014_q4a_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob061_2014_q4a_ifc.txt",
"file_size": 95
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_453
|
Prob110_fsm2_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input j,
input k,
input areset,
output out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob110_fsm2_ifc.txt",
"file_size": 87
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_454
|
Prob089_ece241_2014_q5a_prompt.txt
|
code_completion
|
You are to design a one-input one-output serial 2's complementer Moore
state machine. The input (x) is a series of bits (one per clock cycle)
beginning with the least-significant bit of the number, and the output
(Z) is the 2's complement of the input. The machine will accept input
numbers of arbitrary length. The circuit requires a positive edge
triggered asynchronous reset. The conversion begins when Reset is
released and stops when Reset is asserted.
module TopModule (
input clk,
input areset,
input x,
output z
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob089_ece241_2014_q5a_prompt.txt",
"file_size": 534
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_455
|
Prob149_ece241_2013_q4_prompt.txt
|
code_completion
|
A large reservior of water serves several users. In order to keep the
level of water succificently high, three sensors are placed vertically at
5-inch intervals. When the water level is above the highest sensor s[3],
the input flow rate should be zero. When the level is below the lowest
sensor s[1], the flow rate should be at maximum (both Nominal flow valve
and Supplemental flow valve opened). The flow rate when the level is
between the upper and lower sensors is determined by two factors: the
water level and the level previous to the last sensor change. Each water
level has a nominal flow rate associated with it as show in the table
below. If the sensor change indicates that the previous level was lower
than the current level, the flow rate should be increased by opening the
Supplemental flow valve (controlled by dfr).
Water Level | Sensors Asserted | Nominal Flow Rate Inputs to be Asserted
Above s[3] | s[1], s[2], s[3] | None
Between s[3] and s[2] | s[1], s[2] | fr1
Between s[2] and s[1] | s[1] | fr1, fr2
Below s[1] | None | fr1, fr2, fr3
Also include an active-high synchronous reset that resets the state
machine to a state equivalent to if the water level had been low for a
long time (no sensors asserted, and all four outputs asserted).
module TopModule (
input clk,
input reset,
input [3:1] s,
output reg fr3,
output reg fr2,
output reg fr1,
output reg dfr
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob149_ece241_2013_q4_prompt.txt",
"file_size": 1476
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_456
|
Prob068_countbcd_prompt.txt
|
code_completion
|
Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is
encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit,
etc. For digits [3:1], also output an enable signal indicating when each
of the upper three digits should be incremented. Include a synchronous
active-high reset.
module TopModule (
input clk,
input reset,
output [3:1] ena,
output reg [15:0] q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob068_countbcd_prompt.txt",
"file_size": 406
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_457
|
Prob136_m2014_q6_prompt.txt
|
code_completion
|
Consider the state machine shown below:
A (0) --0--> B
A (0) --1--> A
B (0) --0--> C
B (0) --1--> D
C (0) --0--> E
C (0) --1--> D
D (0) --0--> F
D (0) --1--> A
E (1) --0--> E
E (1) --1--> D
F (1) --0--> C
F (1) --1--> D
Implement this state machine in Verilog.
module TopModule (
input clk,
input reset,
input w,
output z
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob136_m2014_q6_prompt.txt",
"file_size": 362
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_458
|
Prob008_m2014_q4h_prompt.txt
|
code_completion
|
The module assigns the output port to the same value as the input port
combinationally.
module TopModule (
input in,
output out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob008_m2014_q4h_prompt.txt",
"file_size": 138
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_459
|
Prob123_bugs_addsubz_prompt.txt
|
code_completion
|
The following adder-subtractor with zero flag doesn't work. Fix the
bug(s).
synthesis verilog_input_version verilog_2001
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);
always @(*) begin
case (do_sub)
0: out = a+b;
1: out = a-b;
endcase
if (~out)
result_is_zero = 1;
end
endmodule
module TopModule (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob123_bugs_addsubz_prompt.txt",
"file_size": 597
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_460
|
Prob031_dff_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input d,
output reg q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob031_dff_ifc.txt",
"file_size": 62
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_461
|
Prob023_vector100r_ifc.txt
|
code_completion
|
module TopModule (
input [99:0] in,
output reg [99:0] out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob023_vector100r_ifc.txt",
"file_size": 66
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_462
|
Prob067_countslow_prompt.txt
|
code_completion
|
Build a decade counter that counts from 0 through 9, inclusive, with a
period of 10. The reset input is active high synchronous, and should
reset the counter to 0. We want to be able to pause the counter rather
than always incrementing every clock cycle, so the "slowena" input if
high indicates when the counter should increment.
module TopModule (
input clk,
input slowena,
input reset,
output reg [3:0] q
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob067_countslow_prompt.txt",
"file_size": 422
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_463
|
Prob127_lemmings1_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input areset,
input bump_left,
input bump_right,
output walk_left,
output walk_right
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob127_lemmings1_ifc.txt",
"file_size": 131
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_464
|
Prob094_gatesv_prompt.txt
|
code_completion
|
You are given a four-bit input vector in[3:0]. We want to know some
relationships between each bit and its neighbour:
(1) out_both: Each bit of this output vector should indicate whether
both the corresponding input bit and its neighbour to the left (higher
index) are '1'. For example, out_both[2] should indicate if in[2] and
in[3] are both 1. Since in[3] has no neighbour to the left, the answer
is obvious so we don't need to know out_both[3].
(2) out_any: Each bit of this output vector should indicate whether any
of the corresponding input bit and its neighbour to the right are '1'.
For example, out_any[2] should indicate if either in[2] or in[1] are 1.
Since in[0] has no neighbour to the right, the answer is obvious so we
don't need to know out_any[0].
(3) out_different: Each bit of this output vector should indicate
whether the corresponding input bit is different from its neighbour to
the left. For example, out_different[2] should indicate if in[2] is
different from in[3]. For this part, treat the vector as wrapping
around, so in[3]'s neighbour to the left is in[0].
module TopModule (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob094_gatesv_prompt.txt",
"file_size": 1241
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_465
|
Prob066_edgecapture_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input reset,
input [31:0] in,
output reg [31:0] out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob066_edgecapture_ifc.txt",
"file_size": 94
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_466
|
Prob025_reduction_prompt.txt
|
code_completion
|
Parity checking is often used as a simple method of detecting errors when
transmitting data through an imperfect channel. Create a circuit that
will compute a parity bit for a 8-bit byte (which will add a 9th bit to
the byte). We will use "even" parity, where the parity bit is just the
XOR of all 8 data bits.
module TopModule (
input [7:0] in,
output parity
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob025_reduction_prompt.txt",
"file_size": 370
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_467
|
Prob060_m2014_q4k_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input resetn,
input in,
output out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob060_m2014_q4k_ifc.txt",
"file_size": 77
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_468
|
Prob109_fsm1_ifc.txt
|
code_completion
|
module TopModule (
input clk,
input in,
input areset,
output out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob109_fsm1_ifc.txt",
"file_size": 77
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_469
|
Prob066_edgecapture_prompt.txt
|
code_completion
|
For each bit in a 32-bit vector, capture when the input signal changes
from 1 in one clock cycle to 0 the next. "Capture" means that the output
will remain 1 until the register is reset (active high synchronous
reset).
module TopModule (
input clk,
input reset,
input [31:0] in,
output reg [31:0] out
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob066_edgecapture_prompt.txt",
"file_size": 315
}
|
verilog_eval_v2
|
dataset_code-complete-iccad2023
|
veval_470
|
Prob113_2012_q1g_ifc.txt
|
code_completion
|
module TopModule (
input [4:1] x,
output logic f
);
|
{
"file_path": "datasets/verilog_eval_v2/dataset_code-complete-iccad2023/Prob113_2012_q1g_ifc.txt",
"file_size": 57
}
|
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