Set single register from GDB hexadecimal string.
        reg parameter is the index of register in targetXML sent to GDB.
775245
def set_register(self, reg, data):
        
        if reg < 0:
            return
        elif reg < len(self._register_list):
            regName = self._register_list[reg].name
            regBits = self._register_list[reg].bitsize
            if regBits == 64:
                value = conversion.hex16_to_u64be(data)
            else:
                value = conversion.hex8_to_u32be(data)
            logging.debug("GDB: write reg %s: 0x%X", regName, value)
            self._context.write_core_register_raw(regName, value)
1157971
def __registerSeqStr():
    """"""
    _SeqStr = lambda self: (self and "[%s]" % (", ".join(map(repr, self)))) or "[]"
    _SeqRepr = lambda self: (self and "[%s]" % (", ".join(map(repr, self)))) or "[]"

    seqs = (StdStringVector, StdLongVector, CommandInfoList,
            AttributeInfoList, AttributeInfoListEx, PipeInfoList,
            DeviceDataHistoryList,
            GroupReplyList, GroupAttrReplyList, GroupCmdReplyList,
            DbData, DbDevInfos, DbDevExportInfos, DbDevImportInfos, DbHistoryList)

    for seq in seqs:
        seq.__str__ = _SeqStr
        seq.__repr__ = _SeqRepr
465761
def get_register_context(self):
        
        logging.debug("GDB getting register context")
        resp = b''
        reg_num_list = [reg.reg_num for reg in self._register_list]
        vals = self._context.read_core_registers_raw(reg_num_list)
        #print("Vals: %s" % vals)
        for reg, regValue in zip(self._register_list, vals):
            if reg.bitsize == 64:
                resp += six.b(conversion.u64_to_hex16le(regValue))
            else:
                resp += six.b(conversion.u32_to_hex8le(regValue))
            logging.debug("GDB reg: %s = 0x%X", reg.name, regValue)

        return resp
816082
def <<( reg )
      raise "not reg #{reg}" unless reg.is_a?(RegisterValue)
      reg_to_slot = Risc.reg_to_slot("#{reg.class_name} -> #{register.class_name}[#{index}]" , reg , register, index)
      builder.add_code(reg_to_slot) if builder
      reg_to_slot
    end
672912
def instruction_COM_register(self, opcode, register):
        
        register.set(self.COM(value=register.value))
883894
def set_register(self, register, value):
        
        context = self.get_context()
        context[register] = value
        self.set_context(context)
1094558
def process_string(self, tag):
        """"""
        tag.set_address(self.string_register.current_address)
        if self.is_sixteen_bit:
            # each string address needs 1 byte = 1/2 an address
            self.string_register.move_to_next_address(1)
            return
        # each string address needs 1 byte = 1 address
        self.string_register.move_to_next_address(1)
499108
def use_reg( type , extra = {} )
      raise "Not type #{type.inspect}" unless type.is_a?(Symbol) or type.is_a?(Parfait::Type)
      if @regs.empty?
        reg = Risc.tmp_reg(type , extra)
      else
        reg = @regs.last.next_reg_use(type , extra)
      end
      @regs << reg
      return reg
    end
495534
def BX(self, params):
        
        Rj = self.get_one_parameter(self.ONE_PARAMETER, params)

        self.check_arguments(LR_or_general_purpose_registers=(Rj,))

        def BX_func():
            self.register['PC'] = self.register[Rj]

        return BX_func
883377
def add_reg_with_block_format
      # ** Data Register 3 **
      # This is dreg
      add_reg :dreg, 0x1000, size: 16 do |reg|
        # This is dreg bit 15
        reg.bit 15,    :bit15, reset: 1
        # **Bit 14** - This does something cool
        #
        # 0 | Coolness is disabled
        # 1 | Coolness is enabled
        reg.bits 14,    :bit14
        # This is dreg bit upper
        reg.bits 13..8, :upper
        # This is dreg bit lower
        # This is dreg bit lower line 2
        reg.bit 7..0,  :lower, writable: false, reset: 0x55
      end

      # This is dreg2
      reg :dreg2, 0x1000, size: 16 do
        # This is dreg2 bit 15
        bit 15,    :bit15, reset: 1
        # This is dreg2 bit upper
        bits 14..8, :upper
        # This is dreg2 bit lower
        # This is dreg2 bit lower line 2
        bit 7..0,  :lower, writable: false, reset: 0x55
      end

      # Finally a test that descriptions can be supplied via the API
      reg :dreg3, 0x1000, size: 16, description: "** Data Register 3 **\nThis is dreg3" do
        bit 15,    :bit15, reset: 1, description: 'This is dreg3 bit 15'
        bit 14, :bit14, description: "**Bit 14** - This does something cool\n\n0 | Coolness is disabled\n1 | Coolness is enabled"
        bits 13..8, :upper, description: 'This is dreg3 bit upper'
        bit 7..0,  :lower, writable: false, reset: 0x55, description: "This is dreg3 bit lower\nThis is dreg3 bit lower line 2"
      end

      reg :dreg4, 0x1000, size: 8, description: "** Data Register 4 **\nThis is dreg4" do
        bit 7..0, :busy, reset: 0x55, description: "**Busy Bits** - These do something super cool\n\n0 | Job0\n1 | Job1\n10 | Job2\n11 | Job3\n100 | Job4\n101 | Job5\n110 | Job6\n111 | Job7\n1000 | Job8\n1001 | Job9\n1010 | Job10\n1011 | Job11\n1100 | Job12\n1101 | Job13\n1110 | Job14\n1111 | Job15\n10000 | Job16\n10001 | Job17\n10010 | Job18"
      end
    end
454875
public Register getRegister(int index) throws IndexOutOfBoundsException {
        if (index < 0) {
            throw new IndexOutOfBoundsException(index + " < 0");
        }

        if (index >= getWriteWordCount()) {
            throw new IndexOutOfBoundsException(index + " > " + getWriteWordCount());
        }

        return registers[index];
    }
930633
def assemble(io)
      arg = @left
      arg = arg.symbol if( arg.is_a? ::Risc::RegisterValue )
      is_reg = arg.is_a?(::Risc::RegisterValue)
      is_reg = (arg.to_s[0] == "r") if( arg.is_a?(Symbol) and not is_reg)

      raise "invalid operand argument #{arg.inspect} #{inspect}" unless (is_reg )
      operand = get_operand

      #not sure about these 2 constants. They produce the correct output for str r0 , r1
      # but i can't help thinking that that is because they are not used in that instruction and
      # so it doesn't matter. Will see
      if (operand.is_a?(Symbol) or operand.is_a?(::Risc::RegisterValue))
        val = reg_code(operand)
        i = 1  # not quite sure about this, but it gives the output of as. read read read.
      else
        i = 0 #I flag (third bit)
        val = operand
      end
      # testing against gnu as, setting the flag produces correct output
      # but gnu as produces same output for auto_inc or not, so that seems broken
      # luckily auto_inc is not used and even if it clobbers unused reg in soml, but still

      val = shift(val , 0 )
      val |= shift(reg_code(arg) ,  16)
      val |= shift(i ,              25)
      write_val(val, io)
    end
156013
private static String getRegisterName(final Code obj, final int reg) {
        LocalVariableTable lvt = obj.getLocalVariableTable();
        if (lvt != null) {
            LocalVariable lv = lvt.getLocalVariable(reg, 0);
            if (lv != null) {
                return lv.getName();
            }
        }
        return String.valueOf(reg);
    }
284975
private void setXPathCharacteristics(IdentifierImpl identifier)
    throws InvalidXPathSyntaxException
  {
    if (TraceComponent.isAnyTracingEnabled() && tc.isEntryEnabled())
      tc.entry(cclass,
               "setXPathCharacteristics",
               "identifier: " + identifier);
    
    // Need to set the domain to XPATH1.0
    identifier.setSelectorDomain(2);

    // Set the locationStep also
    identifier.setStep(locationStep);
    
    // Call XPath to compile the XPath1.0 expression and store the
    // resultant XPathExpression in the Identifier.
    XPathExpression xpexp = null;
    
    try
    {
      // Parse an expression up-front
      Node node = null;
      NodeList ns = null;
      XPath xpath0 = XPathFactory.newInstance().newXPath();
      
      // If a namespace context has been set then set it into the XPath env
      if(namespaceContext != null)
        xpath0.setNamespaceContext(namespaceContext);
      
      xpexp = xpath0.compile(identifier.getName());
    }
    catch (Exception ex)
    {
      // No FFDC Code Needed.
      // We don't FFDC because we'll catch this exception and then attempt
      // to parse the entire expression. If that fails, then we FFDC.
 
      if (TraceComponent.isAnyTracingEnabled() && tc.isEntryEnabled())
        tc.exit(this,cclass, "setXPathCharacteristics", ex);   
     
      throw new InvalidXPathSyntaxException(identifier.getName());
    }

    // Store xpexp in the Identifier    
    identifier.setCompiledExpression(xpexp);
    
    if (TraceComponent.isAnyTracingEnabled() && tc.isEntryEnabled())
      tc.exit(this,cclass, "setXPathCharacteristics");     
  }
134303
def write_core_registers_raw(self, reg_list, data_list):
        
        assert len(reg_list) == len(data_list)
        # convert to index only
        reg_list = [register_name_to_index(reg) for reg in reg_list]

        # Sanity check register values
        for reg in reg_list:
            if reg not in CORE_REGISTER.values():
                raise ValueError("unknown reg: %d" % reg)
            elif is_fpu_register(reg) and (not self.has_fpu):
                raise ValueError("attempt to write FPU register without FPU")

        # Read special register if it is present in the list and
        # convert doubles to single float register writes.
        cfbpValue = None
        xpsrValue = None
        reg_data_list = []
        for reg, data in zip(reg_list, data_list):
            if is_double_float_register(reg):
                # Replace double with two single float register writes. For instance,
                # a write of D2 gets converted to writes to S4 and S5.
                singleLow = data & 0xffffffff
                singleHigh = (data >> 32) & 0xffffffff
                reg_data_list += [(-reg, singleLow), (-reg + 1, singleHigh)]
            elif is_cfbp_subregister(reg) and cfbpValue is None:
                cfbpValue = self.read_core_register_raw(CORE_REGISTER['cfbp'])
            elif is_psr_subregister(reg) and xpsrValue is None:
                xpsrValue = self.read_core_register_raw(CORE_REGISTER['xpsr'])
            else:
                # Other register, just copy directly.
                reg_data_list.append((reg, data))
        
        # Write out registers
        dhcsr_cb_list = []
        for reg, data in reg_data_list:
            if is_cfbp_subregister(reg):
                # Mask in the new special register value so we don't modify the other register
                # values that share the same DCRSR number.
                shift = (-reg - 1) * 8
                mask = 0xffffffff ^ (0xff << shift)
                data = (cfbpValue & mask) | ((data & 0xff) << shift)
                cfbpValue = data # update special register for other writes that might be in the list
                reg = CORE_REGISTER['cfbp']
            elif is_psr_subregister(reg):
                mask = sysm_to_psr_mask(reg)
                data = (xpsrValue & (0xffffffff ^ mask)) | (data & mask)
                xpsrValue = data
                reg = CORE_REGISTER['xpsr']

            # write DCRDR
            self.write_memory(CortexM.DCRDR, data)

            # write id in DCRSR and flag to start write transfer
            self.write_memory(CortexM.DCRSR, reg | CortexM.DCRSR_REGWnR)

            # Technically, we need to poll S_REGRDY in DHCSR here to ensure the
            # register write has completed.
            # Read it and assert that S_REGRDY is set
            dhcsr_cb = self.read_memory(CortexM.DHCSR, now=False)
            dhcsr_cb_list.append(dhcsr_cb)

        # Make sure S_REGRDY was set for all register
        # writes
        for dhcsr_cb in dhcsr_cb_list:
            dhcsr_val = dhcsr_cb()
            assert dhcsr_val & CortexM.S_REGRDY
1351423
def mask_write_register(addr, and_mask, or_mask)
      query("\x16" + addr.to_word + and_mask.to_word + or_mask.to_word)
      self
    end
1362785
public ChainingXmlWriter register(String parameterName, ICalDataType dataType) {
		parameterDataTypes.put(parameterName, dataType);
		return this;
	}