We are currently solving the following issue within our repository. Here is the issue text:
--- BEGIN ISSUE ---
`context` gives wrong jump target for `jalr ra, ra, -0x16` in RISC-V
The jump target shown as annotation in the disassembly window is wrong:

```c++
pwndbg> si
pwndbg> set emulate on
pwndbg> context
 ► 0x1008e <_start+4>    jalr   ra, ra, -0x16               <main+8>
pwndbg> si
pwndbg> context
 ► 0x10074 <main>    addi   a7, zero, 0x40
```

Interestingly, `nearpc` shows the correct jump target:
```c++
 ► 0x1008e <_start+4>    jalr   ra, ra, -0x16               <main>
 ```
A workaround is `set emulate off`.


### test binary
[Download test binary](https://github.com/pwndbg/pwndbg/files/15366965/riscv-emu-bug.bin.txt). I created it from:

```asm
# riscv32-unknown-linux-gnu-as -march=rv32imac2p0 -o riscv-emu-bug.o riscv-emu-bug.s
# riscv32-unknown-linux-gnu-ld --no-relax -o riscv-emu-bug riscv-emu-bug.o

.section .rodata

greeting: .asciz "Hello world\n"
.equ greetlen, . - greeting

.section .text
main:
        li  a7, 64         # write
        li  a0, 1
        la  a1, greeting
        li  a2, greetlen
        ecall
        ret

.global _start
_start:
        call main
        li  a7, 93         # exit
        li  a0, 0
        ecall
```


### version information

pwndbg version: a1ddb3c0cd5e480710aa48f04ac560d659731bd8 (my fork)
```
Platform: Linux-6.9.1-arch1-1-x86_64-with-glibc2.39
OS: Arch Linux
OS ABI: #1 SMP PREEMPT_DYNAMIC Fri, 17 May 2024 16:56:38 +0000
Architecture: x86_64
Endian: little
Charset: utf-8
Width: 119
Height: 58
Gdb:      14.2
Python:   3.12.3 (main, Apr 23 2024, 09:16:07) [GCC 13.2.1 20240417]
Pwndbg:   2024.02.14 build: a1ddb3c0
Capstone: 5.0.1280
Unicorn:  2.0.1
This GDB was configured as follows:
   configure --host=x86_64-pc-linux-gnu --target=x86_64-pc-linux-gnu
	    --with-auto-load-dir=$debugdir:$datadir/auto-load
	    --with-auto-load-safe-path=$debugdir:$datadir/auto-load
	    --with-expat
	    --with-gdb-datadir=/build/share/gdb (relocatable)
	    --with-jit-reader-dir=/build/lib/gdb (relocatable)
	    --without-libunwind-ia64
	    --with-lzma
	    --without-babeltrace
	    --without-intel-pt
	    --with-xxhash
	    --with-python=/usr
	    --with-python-libdir=/usr/lib
	    --with-debuginfod
	    --with-curses
	    --with-guile
	    --without-amd-dbgapi
	    --enable-source-highlight
	    --enable-threading
	    --enable-tui
	    --with-system-readline
	    --with-separate-debug-dir=/build/lib/debug (relocatable)
	    --with-system-gdbinit=/etc/gdb/gdbinit
```


--- END ISSUE ---

Below are some code segments, each from a relevant file. One or more of these files may contain bugs.
--- BEGIN FILES ---
Path: `pwndbg/disasm/riscv.py`
Content:
```
1 from __future__ import annotations
2 
3 from capstone import *  # noqa: F403
4 from capstone.riscv import *  # noqa: F403
5 
6 import pwndbg.disasm.arch
7 import pwndbg.gdblib.arch
8 import pwndbg.gdblib.regs
9 from pwndbg.disasm.instruction import InstructionCondition
10 from pwndbg.disasm.instruction import PwndbgInstruction
11 from pwndbg.emu.emulator import Emulator
12 
13 
14 class DisassemblyAssistant(pwndbg.disasm.arch.DisassemblyAssistant):
15     def __init__(self, architecture) -> None:
16         super().__init__(architecture)
17         self.architecture = architecture
18 
19     def _is_condition_taken(
20         self, instruction: PwndbgInstruction, emu: Emulator | None
21     ) -> InstructionCondition:
22         # B-type instructions have two source registers that are compared
23         src1_unsigned = self.parse_register(instruction, instruction.op_find(CS_OP_REG, 1), emu)
24         # compressed instructions c.beqz and c.bnez only use one register operand.
25         if instruction.op_count(CS_OP_REG) > 1:
26             src2_unsigned = self.parse_register(instruction, instruction.op_find(CS_OP_REG, 2), emu)
27         else:
28             src2_unsigned = 0
29 
30         if self.architecture == "rv32":
31             src1_signed = src1_unsigned - ((src1_unsigned & 0x80000000) << 1)
32             src2_signed = src2_unsigned - ((src2_unsigned & 0x80000000) << 1)
33         elif self.architecture == "rv64":
34             src1_signed = src1_unsigned - ((src1_unsigned & 0x80000000_00000000) << 1)
35             src2_signed = src2_unsigned - ((src2_unsigned & 0x80000000_00000000) << 1)
36         else:
37             raise NotImplementedError(f"architecture '{self.architecture}' not implemented")
38 
39         condition = {
40             RISCV_INS_BEQ: src1_signed == src2_signed,
41             RISCV_INS_BNE: src1_signed != src2_signed,
42             RISCV_INS_BLT: src1_signed < src2_signed,
43             RISCV_INS_BGE: src1_signed >= src2_signed,
44             RISCV_INS_BLTU: src1_unsigned < src2_unsigned,
45             RISCV_INS_BGEU: src1_unsigned >= src2_unsigned,
46             RISCV_INS_C_BEQZ: src1_signed == 0,
47             RISCV_INS_C_BNEZ: src1_signed != 0,
48         }.get(instruction.id, None)
49 
50         if condition is None:
51             return InstructionCondition.UNDETERMINED
52 
53         return InstructionCondition.TRUE if bool(condition) else InstructionCondition.FALSE
54 
55     def condition(self, instruction: PwndbgInstruction, emu: Emulator) -> InstructionCondition:
56         """Checks if the current instruction is a jump that is taken.
57         Returns None if the instruction is executed unconditionally,
58         True if the instruction is executed for sure, False otherwise.
59         """
60         # JAL / JALR is unconditional
61         if RISCV_GRP_CALL in instruction.groups:
62             return InstructionCondition.UNDETERMINED
63 
64         # We can't reason about anything except the current instruction
65         # as the comparison result is dependent on the register state.
66         if instruction.address != pwndbg.gdblib.regs.pc:
67             return InstructionCondition.UNDETERMINED
68 
69         # Determine if the conditional jump is taken
70         if RISCV_GRP_BRANCH_RELATIVE in instruction.groups:
71             return self._is_condition_taken(instruction, emu)
72 
73         return InstructionCondition.UNDETERMINED
74 
75     def resolve_target(self, instruction: PwndbgInstruction, emu: Emulator | None, call=False):
76         """Return the address of the jump / conditional jump,
77         None if the next address is not dependent on instruction.
78         """
79         ptrmask = pwndbg.gdblib.arch.ptrmask
80         # JAL is unconditional and independent of current register status
81         if instruction.id in [RISCV_INS_JAL, RISCV_INS_C_JAL]:
82             # But that doesn't apply to ARM anyways :)
83             return (instruction.address + instruction.op_find(CS_OP_IMM, 1).imm) & ptrmask
84 
85         # We can't reason about anything except the current instruction
86         # as the comparison result is dependent on the register state.
87         if instruction.address != pwndbg.gdblib.regs.pc:
88             return None
89 
90         # Determine if the conditional jump is taken
91         if RISCV_GRP_BRANCH_RELATIVE in instruction.groups and self._is_condition_taken(
92             instruction, emu
93         ):
94             return (instruction.address + instruction.op_find(CS_OP_IMM, 1).imm) & ptrmask
95 
96         # Determine the target address of the indirect jump
97         if instruction.id in [RISCV_INS_JALR, RISCV_INS_C_JALR]:
98             target = (
99                 self.parse_register(instruction, instruction.op_find(CS_OP_REG, 1), emu)
100                 + instruction.op_find(CS_OP_IMM, 1).imm
101             ) & ptrmask
102             # Clear the lowest bit without knowing the register width
103             return target ^ (target & 1)
104 
105         return super().resolve_target(instruction, emu, call)
106 
107 
108 assistant_rv32 = DisassemblyAssistant("rv32")
109 assistant_rv64 = DisassemblyAssistant("rv64")
110
```
--- END FILES ---

Please first localize the bug based on the issue statement, and then generate a patch according to the `git diff` format fenced by three backticks.

Here is an example:

```diff
diff --git a/examples/server_async.py b/examples/server_async.py
--- a/examples/server_async.py
+++ b/examples/server_async.py
@@ -313,4 +313,4 @@
 
 
 if __name__ == "__main__":
-    asyncio.run(run_async_server("."), debug=True)
+    asyncio.run(run_async_server(), debug=True)
diff --git a/examples/server_sync.py b/examples/server_sync.py
--- a/examples/server_sync.py
+++ b/examples/server_sync.py
@@ -313,5 +313,5 @@
 
 
 if __name__ == "__main__":
-    server = run_sync_server(".")
+    server = run_sync_server()
     server.shutdown()

```

diff --git a/pwndbg/disasm/riscv.py b/pwndbg/disasm/riscv.py
--- a/pwndbg/disasm/riscv.py
+++ b/pwndbg/disasm/riscv.py
@@ -20,10 +20,10 @@
         self, instruction: PwndbgInstruction, emu: Emulator | None
     ) -> InstructionCondition:
         # B-type instructions have two source registers that are compared
-        src1_unsigned = self.parse_register(instruction, instruction.op_find(CS_OP_REG, 1), emu)
+        src1_unsigned = instruction.op_find(CS_OP_REG, 1).before_value
         # compressed instructions c.beqz and c.bnez only use one register operand.
         if instruction.op_count(CS_OP_REG) > 1:
-            src2_unsigned = self.parse_register(instruction, instruction.op_find(CS_OP_REG, 2), emu)
+            src2_unsigned = instruction.op_find(CS_OP_REG, 2).before_value
         else:
             src2_unsigned = 0
 
@@ -96,7 +96,7 @@
         # Determine the target address of the indirect jump
         if instruction.id in [RISCV_INS_JALR, RISCV_INS_C_JALR]:
             target = (
-                self.parse_register(instruction, instruction.op_find(CS_OP_REG, 1), emu)
+                instruction.op_find(CS_OP_REG, 1).before_value
                 + instruction.op_find(CS_OP_IMM, 1).imm
             ) & ptrmask
             # Clear the lowest bit without knowing the register width

{"golden_diff": "diff --git a/pwndbg/disasm/riscv.py b/pwndbg/disasm/riscv.py\n--- a/pwndbg/disasm/riscv.py\n+++ b/pwndbg/disasm/riscv.py\n@@ -20,10 +20,10 @@\n         self, instruction: PwndbgInstruction, emu: Emulator | None\n     ) -> InstructionCondition:\n         # B-type instructions have two source registers that are compared\n-        src1_unsigned = self.parse_register(instruction, instruction.op_find(CS_OP_REG, 1), emu)\n+        src1_unsigned = instruction.op_find(CS_OP_REG, 1).before_value\n         # compressed instructions c.beqz and c.bnez only use one register operand.\n         if instruction.op_count(CS_OP_REG) > 1:\n-            src2_unsigned = self.parse_register(instruction, instruction.op_find(CS_OP_REG, 2), emu)\n+            src2_unsigned = instruction.op_find(CS_OP_REG, 2).before_value\n         else:\n             src2_unsigned = 0\n \n@@ -96,7 +96,7 @@\n         # Determine the target address of the indirect jump\n         if instruction.id in [RISCV_INS_JALR, RISCV_INS_C_JALR]:\n             target = (\n-                self.parse_register(instruction, instruction.op_find(CS_OP_REG, 1), emu)\n+                instruction.op_find(CS_OP_REG, 1).before_value\n                 + instruction.op_find(CS_OP_IMM, 1).imm\n             ) & ptrmask\n             # Clear the lowest bit without knowing the register width\n", "issue": "`context` gives wrong jump target for `jalr ra, ra, -0x16` in RISC-V\nThe jump target shown as annotation in the disassembly window is wrong:\r\n\r\n```c++\r\npwndbg> si\r\npwndbg> set emulate on\r\npwndbg> context\r\n \u25ba 0x1008e <_start+4>    jalr   ra, ra, -0x16               <main+8>\r\npwndbg> si\r\npwndbg> context\r\n \u25ba 0x10074 <main>    addi   a7, zero, 0x40\r\n```\r\n\r\nInterestingly, `nearpc` shows the correct jump target:\r\n```c++\r\n \u25ba 0x1008e <_start+4>    jalr   ra, ra, -0x16               <main>\r\n ```\r\nA workaround is `set emulate off`.\r\n\r\n\r\n### test binary\r\n[Download test binary](https://github.com/pwndbg/pwndbg/files/15366965/riscv-emu-bug.bin.txt). I created it from:\r\n\r\n```asm\r\n# riscv32-unknown-linux-gnu-as -march=rv32imac2p0 -o riscv-emu-bug.o riscv-emu-bug.s\r\n# riscv32-unknown-linux-gnu-ld --no-relax -o riscv-emu-bug riscv-emu-bug.o\r\n\r\n.section .rodata\r\n\r\ngreeting: .asciz \"Hello world\\n\"\r\n.equ greetlen, . - greeting\r\n\r\n.section .text\r\nmain:\r\n        li  a7, 64         # write\r\n        li  a0, 1\r\n        la  a1, greeting\r\n        li  a2, greetlen\r\n        ecall\r\n        ret\r\n\r\n.global _start\r\n_start:\r\n        call main\r\n        li  a7, 93         # exit\r\n        li  a0, 0\r\n        ecall\r\n```\r\n\r\n\r\n### version information\r\n\r\npwndbg version: a1ddb3c0cd5e480710aa48f04ac560d659731bd8 (my fork)\r\n```\r\nPlatform: Linux-6.9.1-arch1-1-x86_64-with-glibc2.39\r\nOS: Arch Linux\r\nOS ABI: #1 SMP PREEMPT_DYNAMIC Fri, 17 May 2024 16:56:38 +0000\r\nArchitecture: x86_64\r\nEndian: little\r\nCharset: utf-8\r\nWidth: 119\r\nHeight: 58\r\nGdb:      14.2\r\nPython:   3.12.3 (main, Apr 23 2024, 09:16:07) [GCC 13.2.1 20240417]\r\nPwndbg:   2024.02.14 build: a1ddb3c0\r\nCapstone: 5.0.1280\r\nUnicorn:  2.0.1\r\nThis GDB was configured as follows:\r\n   configure --host=x86_64-pc-linux-gnu --target=x86_64-pc-linux-gnu\r\n\t    --with-auto-load-dir=$debugdir:$datadir/auto-load\r\n\t    --with-auto-load-safe-path=$debugdir:$datadir/auto-load\r\n\t    --with-expat\r\n\t    --with-gdb-datadir=/build/share/gdb (relocatable)\r\n\t    --with-jit-reader-dir=/build/lib/gdb (relocatable)\r\n\t    --without-libunwind-ia64\r\n\t    --with-lzma\r\n\t    --without-babeltrace\r\n\t    --without-intel-pt\r\n\t    --with-xxhash\r\n\t    --with-python=/usr\r\n\t    --with-python-libdir=/usr/lib\r\n\t    --with-debuginfod\r\n\t    --with-curses\r\n\t    --with-guile\r\n\t    --without-amd-dbgapi\r\n\t    --enable-source-highlight\r\n\t    --enable-threading\r\n\t    --enable-tui\r\n\t    --with-system-readline\r\n\t    --with-separate-debug-dir=/build/lib/debug (relocatable)\r\n\t    --with-system-gdbinit=/etc/gdb/gdbinit\r\n```\r\n\n", "before_files": [{"content": "from __future__ import annotations\n\nfrom capstone import *  # noqa: F403\nfrom capstone.riscv import *  # noqa: F403\n\nimport pwndbg.disasm.arch\nimport pwndbg.gdblib.arch\nimport pwndbg.gdblib.regs\nfrom pwndbg.disasm.instruction import InstructionCondition\nfrom pwndbg.disasm.instruction import PwndbgInstruction\nfrom pwndbg.emu.emulator import Emulator\n\n\nclass DisassemblyAssistant(pwndbg.disasm.arch.DisassemblyAssistant):\n    def __init__(self, architecture) -> None:\n        super().__init__(architecture)\n        self.architecture = architecture\n\n    def _is_condition_taken(\n        self, instruction: PwndbgInstruction, emu: Emulator | None\n    ) -> InstructionCondition:\n        # B-type instructions have two source registers that are compared\n        src1_unsigned = self.parse_register(instruction, instruction.op_find(CS_OP_REG, 1), emu)\n        # compressed instructions c.beqz and c.bnez only use one register operand.\n        if instruction.op_count(CS_OP_REG) > 1:\n            src2_unsigned = self.parse_register(instruction, instruction.op_find(CS_OP_REG, 2), emu)\n        else:\n            src2_unsigned = 0\n\n        if self.architecture == \"rv32\":\n            src1_signed = src1_unsigned - ((src1_unsigned & 0x80000000) << 1)\n            src2_signed = src2_unsigned - ((src2_unsigned & 0x80000000) << 1)\n        elif self.architecture == \"rv64\":\n            src1_signed = src1_unsigned - ((src1_unsigned & 0x80000000_00000000) << 1)\n            src2_signed = src2_unsigned - ((src2_unsigned & 0x80000000_00000000) << 1)\n        else:\n            raise NotImplementedError(f\"architecture '{self.architecture}' not implemented\")\n\n        condition = {\n            RISCV_INS_BEQ: src1_signed == src2_signed,\n            RISCV_INS_BNE: src1_signed != src2_signed,\n            RISCV_INS_BLT: src1_signed < src2_signed,\n            RISCV_INS_BGE: src1_signed >= src2_signed,\n            RISCV_INS_BLTU: src1_unsigned < src2_unsigned,\n            RISCV_INS_BGEU: src1_unsigned >= src2_unsigned,\n            RISCV_INS_C_BEQZ: src1_signed == 0,\n            RISCV_INS_C_BNEZ: src1_signed != 0,\n        }.get(instruction.id, None)\n\n        if condition is None:\n            return InstructionCondition.UNDETERMINED\n\n        return InstructionCondition.TRUE if bool(condition) else InstructionCondition.FALSE\n\n    def condition(self, instruction: PwndbgInstruction, emu: Emulator) -> InstructionCondition:\n        \"\"\"Checks if the current instruction is a jump that is taken.\n        Returns None if the instruction is executed unconditionally,\n        True if the instruction is executed for sure, False otherwise.\n        \"\"\"\n        # JAL / JALR is unconditional\n        if RISCV_GRP_CALL in instruction.groups:\n            return InstructionCondition.UNDETERMINED\n\n        # We can't reason about anything except the current instruction\n        # as the comparison result is dependent on the register state.\n        if instruction.address != pwndbg.gdblib.regs.pc:\n            return InstructionCondition.UNDETERMINED\n\n        # Determine if the conditional jump is taken\n        if RISCV_GRP_BRANCH_RELATIVE in instruction.groups:\n            return self._is_condition_taken(instruction, emu)\n\n        return InstructionCondition.UNDETERMINED\n\n    def resolve_target(self, instruction: PwndbgInstruction, emu: Emulator | None, call=False):\n        \"\"\"Return the address of the jump / conditional jump,\n        None if the next address is not dependent on instruction.\n        \"\"\"\n        ptrmask = pwndbg.gdblib.arch.ptrmask\n        # JAL is unconditional and independent of current register status\n        if instruction.id in [RISCV_INS_JAL, RISCV_INS_C_JAL]:\n            # But that doesn't apply to ARM anyways :)\n            return (instruction.address + instruction.op_find(CS_OP_IMM, 1).imm) & ptrmask\n\n        # We can't reason about anything except the current instruction\n        # as the comparison result is dependent on the register state.\n        if instruction.address != pwndbg.gdblib.regs.pc:\n            return None\n\n        # Determine if the conditional jump is taken\n        if RISCV_GRP_BRANCH_RELATIVE in instruction.groups and self._is_condition_taken(\n            instruction, emu\n        ):\n            return (instruction.address + instruction.op_find(CS_OP_IMM, 1).imm) & ptrmask\n\n        # Determine the target address of the indirect jump\n        if instruction.id in [RISCV_INS_JALR, RISCV_INS_C_JALR]:\n            target = (\n                self.parse_register(instruction, instruction.op_find(CS_OP_REG, 1), emu)\n                + instruction.op_find(CS_OP_IMM, 1).imm\n            ) & ptrmask\n            # Clear the lowest bit without knowing the register width\n            return target ^ (target & 1)\n\n        return super().resolve_target(instruction, emu, call)\n\n\nassistant_rv32 = DisassemblyAssistant(\"rv32\")\nassistant_rv64 = DisassemblyAssistant(\"rv64\")\n", "path": "pwndbg/disasm/riscv.py"}], "after_files": [{"content": "from __future__ import annotations\n\nfrom capstone import *  # noqa: F403\nfrom capstone.riscv import *  # noqa: F403\n\nimport pwndbg.disasm.arch\nimport pwndbg.gdblib.arch\nimport pwndbg.gdblib.regs\nfrom pwndbg.disasm.instruction import InstructionCondition\nfrom pwndbg.disasm.instruction import PwndbgInstruction\nfrom pwndbg.emu.emulator import Emulator\n\n\nclass DisassemblyAssistant(pwndbg.disasm.arch.DisassemblyAssistant):\n    def __init__(self, architecture) -> None:\n        super().__init__(architecture)\n        self.architecture = architecture\n\n    def _is_condition_taken(\n        self, instruction: PwndbgInstruction, emu: Emulator | None\n    ) -> InstructionCondition:\n        # B-type instructions have two source registers that are compared\n        src1_unsigned = instruction.op_find(CS_OP_REG, 1).before_value\n        # compressed instructions c.beqz and c.bnez only use one register operand.\n        if instruction.op_count(CS_OP_REG) > 1:\n            src2_unsigned = instruction.op_find(CS_OP_REG, 2).before_value\n        else:\n            src2_unsigned = 0\n\n        if self.architecture == \"rv32\":\n            src1_signed = src1_unsigned - ((src1_unsigned & 0x80000000) << 1)\n            src2_signed = src2_unsigned - ((src2_unsigned & 0x80000000) << 1)\n        elif self.architecture == \"rv64\":\n            src1_signed = src1_unsigned - ((src1_unsigned & 0x80000000_00000000) << 1)\n            src2_signed = src2_unsigned - ((src2_unsigned & 0x80000000_00000000) << 1)\n        else:\n            raise NotImplementedError(f\"architecture '{self.architecture}' not implemented\")\n\n        condition = {\n            RISCV_INS_BEQ: src1_signed == src2_signed,\n            RISCV_INS_BNE: src1_signed != src2_signed,\n            RISCV_INS_BLT: src1_signed < src2_signed,\n            RISCV_INS_BGE: src1_signed >= src2_signed,\n            RISCV_INS_BLTU: src1_unsigned < src2_unsigned,\n            RISCV_INS_BGEU: src1_unsigned >= src2_unsigned,\n            RISCV_INS_C_BEQZ: src1_signed == 0,\n            RISCV_INS_C_BNEZ: src1_signed != 0,\n        }.get(instruction.id, None)\n\n        if condition is None:\n            return InstructionCondition.UNDETERMINED\n\n        return InstructionCondition.TRUE if bool(condition) else InstructionCondition.FALSE\n\n    def condition(self, instruction: PwndbgInstruction, emu: Emulator) -> InstructionCondition:\n        \"\"\"Checks if the current instruction is a jump that is taken.\n        Returns None if the instruction is executed unconditionally,\n        True if the instruction is executed for sure, False otherwise.\n        \"\"\"\n        # JAL / JALR is unconditional\n        if RISCV_GRP_CALL in instruction.groups:\n            return InstructionCondition.UNDETERMINED\n\n        # We can't reason about anything except the current instruction\n        # as the comparison result is dependent on the register state.\n        if instruction.address != pwndbg.gdblib.regs.pc:\n            return InstructionCondition.UNDETERMINED\n\n        # Determine if the conditional jump is taken\n        if RISCV_GRP_BRANCH_RELATIVE in instruction.groups:\n            return self._is_condition_taken(instruction, emu)\n\n        return InstructionCondition.UNDETERMINED\n\n    def resolve_target(self, instruction: PwndbgInstruction, emu: Emulator | None, call=False):\n        \"\"\"Return the address of the jump / conditional jump,\n        None if the next address is not dependent on instruction.\n        \"\"\"\n        ptrmask = pwndbg.gdblib.arch.ptrmask\n        # JAL is unconditional and independent of current register status\n        if instruction.id in [RISCV_INS_JAL, RISCV_INS_C_JAL]:\n            # But that doesn't apply to ARM anyways :)\n            return (instruction.address + instruction.op_find(CS_OP_IMM, 1).imm) & ptrmask\n\n        # We can't reason about anything except the current instruction\n        # as the comparison result is dependent on the register state.\n        if instruction.address != pwndbg.gdblib.regs.pc:\n            return None\n\n        # Determine if the conditional jump is taken\n        if RISCV_GRP_BRANCH_RELATIVE in instruction.groups and self._is_condition_taken(\n            instruction, emu\n        ):\n            return (instruction.address + instruction.op_find(CS_OP_IMM, 1).imm) & ptrmask\n\n        # Determine the target address of the indirect jump\n        if instruction.id in [RISCV_INS_JALR, RISCV_INS_C_JALR]:\n            target = (\n                instruction.op_find(CS_OP_REG, 1).before_value\n                + instruction.op_find(CS_OP_IMM, 1).imm\n            ) & ptrmask\n            # Clear the lowest bit without knowing the register width\n            return target ^ (target & 1)\n\n        return super().resolve_target(instruction, emu, call)\n\n\nassistant_rv32 = DisassemblyAssistant(\"rv32\")\nassistant_rv64 = DisassemblyAssistant(\"rv64\")\n", "path": "pwndbg/disasm/riscv.py"}]}