board.v
sys_clk_gen.v

sys_clk_gen_ds.v

../dsport/xilinx_pcie_2_1_rport_7x.v
../dsport/pcie_2_1_rport_7x.v
../dsport/pcie_axi_trn_bridge.v
../dsport/pci_exp_usrapp_com.v
../dsport/pci_exp_usrapp_tx.v
../dsport/pci_exp_usrapp_cfg.v
../dsport/pci_exp_usrapp_rx.v
../dsport/pci_exp_usrapp_pl.v

../../source/pcieCore_gt_rx_valid_filter_7x.v
../../source/pcieCore_gt_top.v
../../source/pcieCore_pcie_bram_top_7x.v
../../source/pcieCore_pcie_brams_7x.v
../../source/pcieCore_pcie_bram_7x.v
../../source/pcieCore_pcie_7x.v
../../source/pcieCore_pcie_pipe_pipeline.v
../../source/pcieCore_pcie_pipe_lane.v
../../source/pcieCore_pcie_pipe_misc.v
../../source/pcieCore_axi_basic_tx_thrtl_ctl.v
../../source/pcieCore_axi_basic_rx.v
../../source/pcieCore_axi_basic_rx_null_gen.v
../../source/pcieCore_axi_basic_rx_pipeline.v
../../source/pcieCore_axi_basic_tx_pipeline.v
../../source/pcieCore_axi_basic_tx.v
../../source/pcieCore_axi_basic_top.v
../../source/pcieCore_pcie_top.v
../../source/pcieCore.v

../../source/pcieCore_gt_wrapper.v
../../source/pcieCore_gtp_pipe_rate.v
../../source/pcieCore_gtp_pipe_reset.v
../../source/pcieCore_gtp_pipe_drp.v
../../source/pcieCore_qpll_wrapper.v
../../source/pcieCore_qpll_drp.v
../../source/pcieCore_qpll_reset.v
../../source/pcieCore_rxeq_scan.v
../../source/pcieCore_pipe_eq.v
../../source/pcieCore_pipe_clock.v
../../source/pcieCore_pipe_drp.v
../../source/pcieCore_pipe_rate.v
../../source/pcieCore_pipe_reset.v
../../source/pcieCore_pipe_user.v
../../source/pcieCore_pipe_sync.v
../../source/pcieCore_pipe_wrapper.v

../../example_design/xilinx_pcie_2_1_ep_7x.v
../../example_design/pcie_app_7x.v
../../example_design/PIO_EP.v
../../example_design/PIO_EP_MEM_ACCESS.v
../../example_design/EP_MEM.v
../../example_design/PIO_RX_ENGINE.v
../../example_design/PIO_TX_ENGINE.v
../../example_design/PIO_TO_CTRL.v
../../example_design/PIO.v
