Add pipeline tag, link to project page
#1
by
nielsr
HF Staff
- opened
README.md
CHANGED
|
@@ -4,9 +4,12 @@ base_model:
|
|
| 4 |
library_name: transformers
|
| 5 |
tags:
|
| 6 |
- verilog
|
|
|
|
| 7 |
---
|
|
|
|
| 8 |
## CodeV-R1-Qwen-7B
|
| 9 |
|
|
|
|
| 10 |
|
| 11 |
### 1. Introduction
|
| 12 |
|
|
@@ -78,7 +81,9 @@ vllm serve zhuyaoyu/CodeV-R1-Distill-Qwen-7B --tensor-parallel-size 2 --max-mode
|
|
| 78 |
During training and evaluation, we use a system prompt
|
| 79 |
|
| 80 |
```
|
| 81 |
-
You are a helpful assistant. The assistant first thinks about the reasoning process in the mind and then provides the user with the answer. The reasoning process and answer are enclosed within <think> </think> and<answer> </answer> tags, respectively, i.e., <think> reasoning process here </think><answer> answer here </answer>. Now the user asks you to write verilog code. After thinking, when you finally reach a conclusion, enclose the final verilog code in ```verilog ``` within <answer> </answer> tags. i.e., <answer> ```verilog
|
|
|
|
|
|
|
| 82 |
```
|
| 83 |
|
| 84 |
It is recommended to use this prompt during inference.
|
|
|
|
| 4 |
library_name: transformers
|
| 5 |
tags:
|
| 6 |
- verilog
|
| 7 |
+
pipeline_tag: text-generation
|
| 8 |
---
|
| 9 |
+
|
| 10 |
## CodeV-R1-Qwen-7B
|
| 11 |
|
| 12 |
+
[Project page](https://iprc-dip.github.io/CodeV-R1)
|
| 13 |
|
| 14 |
### 1. Introduction
|
| 15 |
|
|
|
|
| 81 |
During training and evaluation, we use a system prompt
|
| 82 |
|
| 83 |
```
|
| 84 |
+
You are a helpful assistant. The assistant first thinks about the reasoning process in the mind and then provides the user with the answer. The reasoning process and answer are enclosed within <think> </think> and<answer> </answer> tags, respectively, i.e., <think> reasoning process here </think><answer> answer here </answer>. Now the user asks you to write verilog code. After thinking, when you finally reach a conclusion, enclose the final verilog code in ```verilog ``` within <answer> </answer> tags. i.e., <answer> ```verilog
|
| 85 |
+
module top_module(in, out, ...) ... ``` </answer>.
|
| 86 |
+
|
| 87 |
```
|
| 88 |
|
| 89 |
It is recommended to use this prompt during inference.
|