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Datasets:
AbiralArch
/
hardware-verilogeval-v2
like
0
Tasks:
Text Generation
Modalities:
Text
Formats:
json
Languages:
code
Size:
< 1K
Tags:
hardware
rtl
verilog
systemverilog
fpga
asic
+ 2
Libraries:
Datasets
pandas
Croissant
+ 1
Dataset card
Data Studio
Files
Files and versions
xet
Community
1
d46132c
hardware-verilogeval-v2
408 kB
1 contributor
History:
2 commits
AbiralArch
Upload verilog_eval_problems.json with huggingface_hub
d46132c
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4 months ago
.gitattributes
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2.46 kB
initial commit
4 months ago
verilog_eval_problems.json
Safe
406 kB
Upload verilog_eval_problems.json with huggingface_hub
4 months ago